diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2008-06-09 17:15:00 (GMT) |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-07-08 05:47:18 (GMT) |
| commit | aa276e1cafb3ce9d01d1e837bcd67e92616013ac (patch) | |
| tree | d0ecb8fe8ae70fdaed8d97d317199180882671b5 /include/asm-x86/apic.h | |
| parent | 00dba56465228825ea806e3a7fc0aa6bba7bdc6c (diff) | |
| download | linux-fsl-qoriq-aa276e1cafb3ce9d01d1e837bcd67e92616013ac.tar.xz | |
x86, clockevents: add C1E aware idle function
C1E on AMD machines is like C3 but without control from the OS. Up to
now we disabled the local apic timer for those machines as it stops
when the CPU goes into C1E. This excludes those machines from high
resolution timers / dynamic ticks, which hurts especially X2 based
laptops.
The current boot time C1E detection has another, more serious flaw
as well: some BIOSes do not enable C1E until the ACPI processor module
is loaded. This causes systems to stop working after that point.
To work nicely with C1E enabled machines we use a separate idle
function, which checks on idle entry whether C1E was enabled in the
Interrupt Pending Message MSR. This allows us to do timer broadcasting
for C1E and covers the late enablement of C1E as well.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/apic.h')
| -rw-r--r-- | include/asm-x86/apic.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/include/asm-x86/apic.h b/include/asm-x86/apic.h index be9639a..3c387cd 100644 --- a/include/asm-x86/apic.h +++ b/include/asm-x86/apic.h @@ -38,12 +38,9 @@ extern void generic_apic_probe(void); extern int apic_verbosity; extern int timer_over_8254; extern int local_apic_timer_c2_ok; -extern int local_apic_timer_disabled; -extern int apic_runs_main_timer; extern int ioapic_force; extern int disable_apic; -extern int disable_apic_timer; /* * Basic functions accessing APICs. |