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author | Len Brown <len.brown@intel.com> | 2009-01-09 08:39:43 (GMT) |
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committer | Len Brown <len.brown@intel.com> | 2009-01-09 08:39:43 (GMT) |
commit | b2576e1d4408e134e2188c967b1f28af39cd79d4 (patch) | |
tree | 004f3c82faab760f304ce031d6d2f572e7746a50 /include/asm-xtensa/byteorder.h | |
parent | 3cc8a5f4ba91f67bbdb81a43a99281a26aab8d77 (diff) | |
parent | 2150edc6c5cf00f7adb54538b9ea2a3e9cedca3f (diff) | |
download | linux-fsl-qoriq-b2576e1d4408e134e2188c967b1f28af39cd79d4.tar.xz |
Merge branch 'linus' into release
Diffstat (limited to 'include/asm-xtensa/byteorder.h')
-rw-r--r-- | include/asm-xtensa/byteorder.h | 82 |
1 files changed, 0 insertions, 82 deletions
diff --git a/include/asm-xtensa/byteorder.h b/include/asm-xtensa/byteorder.h deleted file mode 100644 index 765edf1..0000000 --- a/include/asm-xtensa/byteorder.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * include/asm-xtensa/byteorder.h - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001 - 2005 Tensilica Inc. - */ - -#ifndef _XTENSA_BYTEORDER_H -#define _XTENSA_BYTEORDER_H - -#include <asm/types.h> -#include <linux/compiler.h> - -static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) -{ - __u32 res; - /* instruction sequence from Xtensa ISA release 2/2000 */ - __asm__("ssai 8 \n\t" - "srli %0, %1, 16 \n\t" - "src %0, %0, %1 \n\t" - "src %0, %0, %0 \n\t" - "src %0, %1, %0 \n" - : "=&a" (res) - : "a" (x) - ); - return res; -} - -static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) -{ - /* Given that 'short' values are signed (i.e., can be negative), - * we cannot assume that the upper 16-bits of the register are - * zero. We are careful to mask values after shifting. - */ - - /* There exists an anomaly between xt-gcc and xt-xcc. xt-gcc - * inserts an extui instruction after putting this function inline - * to ensure that it uses only the least-significant 16 bits of - * the result. xt-xcc doesn't use an extui, but assumes the - * __asm__ macro follows convention that the upper 16 bits of an - * 'unsigned short' result are still zero. This macro doesn't - * follow convention; indeed, it leaves garbage in the upport 16 - * bits of the register. - - * Declaring the temporary variables 'res' and 'tmp' to be 32-bit - * types while the return type of the function is a 16-bit type - * forces both compilers to insert exactly one extui instruction - * (or equivalent) to mask off the upper 16 bits. */ - - __u32 res; - __u32 tmp; - - __asm__("extui %1, %2, 8, 8\n\t" - "slli %0, %2, 8 \n\t" - "or %0, %0, %1 \n" - : "=&a" (res), "=&a" (tmp) - : "a" (x) - ); - - return res; -} - -#define __arch__swab32(x) ___arch__swab32(x) -#define __arch__swab16(x) ___arch__swab16(x) - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#ifdef __XTENSA_EL__ -# include <linux/byteorder/little_endian.h> -#elif defined(__XTENSA_EB__) -# include <linux/byteorder/big_endian.h> -#else -# error processor byte order undefined! -#endif - -#endif /* _XTENSA_BYTEORDER_H */ |