ARM: ls1021a: add gating clocks to IP blocks.

A given application may not use all the peripherals on the device.
In this case, it may be desirable to disable unused peripherals.
DCFG provides a mechanism for gating clocks to IP blocks that are
not used when running an application.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>

---
This patch has been sent out to the community and under discussion：
URL：http://www.spinics.net/lists/arm-kernel/msg370133.html

Change-Id: Iedf07d12955b3fa011a0bef27236f73405cefb44
Reviewed-on: http://git.am.freescale.net:8181/21604
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>

1 files changed, 55 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/ls1021a-clock.h b/include/dt-bindings/clock/ls1021a-clock.h
new file mode 100644
index 0000000..09b47d7
--- /dev/null
+++ b/include/dt-bindings/clock/ls1021a-clock.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_LS1021A_H
+#define __DT_BINDINGS_CLOCK_LS1021A_H
+
+#define LS1021A_CLK_DUMMY	0
+#define LS1021A_CLK_PBL_EN	1
+#define LS1021A_CLK_ESDHC_EN	2
+#define LS1021A_CLK_DMA1_EN	3
+#define LS1021A_CLK_DMA2_EN	4
+#define LS1021A_CLK_USB3_PHY_EN	5
+#define LS1021A_CLK_USB2_EN	6
+#define LS1021A_CLK_SATA_EN	7
+#define LS1021A_CLK_USB3_EN	8
+#define LS1021A_CLK_SEC_EN	9
+#define LS1021A_CLK_2D_ACE_EN	10
+#define LS1021A_CLK_QE_EN	11
+#define LS1021A_CLK_ETSEC1_EN	12
+#define LS1021A_CLK_ETSEC2_EN	13
+#define LS1021A_CLK_ETSEC3_EN	14
+#define LS1021A_CLK_PEX1_EN	15
+#define LS1021A_CLK_PEX2_EN	16
+#define LS1021A_CLK_DUART1_EN	17
+#define LS1021A_CLK_DUART2_EN	18
+#define LS1021A_CLK_QSPI_EN	19
+#define LS1021A_CLK_DDR_EN	20
+#define LS1021A_CLK_OCRAM1_EN	21
+#define LS1021A_CLK_IFC_EN	22
+#define LS1021A_CLK_GPIO_EN	23
+#define LS1021A_CLK_DBG_EN	24
+#define LS1021A_CLK_FLEXCAN1_EN	25
+#define LS1021A_CLK_FLEXCAN234_EN	26
+#define LS1021A_CLK_FLEXTIMER_EN	27
+#define LS1021A_CLK_SECMON_EN	28
+#define LS1021A_CLK_WDOG_EN	29
+#define LS1021A_CLK_WDOG12_EN	30
+#define LS1021A_CLK_I2C23_EN	31
+#define LS1021A_CLK_SAI_EN	32
+#define LS1021A_CLK_LPUART_EN	33
+#define LS1021A_CLK_DSPI12_EN	34
+#define LS1021A_CLK_ASRC_EN	35
+#define LS1021A_CLK_SPDIF_EN	36
+#define LS1021A_CLK_I2C1_EN	37
+#define LS1021A_CLK_LPUART1_EN	38
+#define LS1021A_CLK_FLEXTIMER1_EN	39
+#define LS1021A_CLK_END		40
+
+#endif /* __DT_BINDINGS_CLOCK_LS1021A_H */