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authorArnd Bergmann <arnd@arndb.de>2013-04-08 16:26:15 (GMT)
committerArnd Bergmann <arnd@arndb.de>2013-04-08 16:26:15 (GMT)
commite9069cf8b74b50d804fd540a9fd1383504f4af93 (patch)
tree0b3a30308ffc00a73f681bfdf19214b5ba9ae5a6 /include/linux/mtd/nand.h
parent4680ebc2c90f663ba70c6bb3d8596b0f2c4dfa9e (diff)
parentce63d6d4bb9f601de32d4b99f925a65182521873 (diff)
downloadlinux-fsl-qoriq-e9069cf8b74b50d804fd540a9fd1383504f4af93.tar.xz
Merge tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt into next/drivers
From Tony Prisk <linux@prisktech.co.nz>: arm: vt8500: Add pinctrl driver for arch-vt8500 This series adds support for the pinctrl/gpio module on all arch-vt8500 supported SoCs. As part of the review process, some tidy up is also done to drivers/of/base.c to remove some code that is being constantly duplicated. Also, a patch for the bcm2835 pinctrl driver is included to take advantage of the new of/base.c code. * tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt: (606 commits) pinctrl: bcm2835: make use of of_property_read_u32_index() gpio: vt8500: Remove arch-vt8500 gpio driver arm: vt8500: Remove gpio devicetree nodes arm: dts: vt8500: Update Wondermedia SoC dtsi files for pinctrl driver pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500 arm: vt8500: Increase available GPIOs on arch-vt8500 of: Remove duplicated code for validating property and value of: Add support for reading a u32 from a multi-value property. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include/linux/mtd/nand.h')
-rw-r--r--include/linux/mtd/nand.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 7ccb3c5..ef52d9c 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -187,6 +187,13 @@ typedef enum {
* This happens with the Renesas AG-AND chips, possibly others.
*/
#define BBT_AUTO_REFRESH 0x00000080
+/*
+ * Chip requires ready check on read (for auto-incremented sequential read).
+ * True only for small page devices; large page devices do not support
+ * autoincrement.
+ */
+#define NAND_NEED_READRDY 0x00000100
+
/* Chip does not allow subpage writes */
#define NAND_NO_SUBPAGE_WRITE 0x00000200