diff options
author | Vipin Kumar <vipin.kumar@st.com> | 2012-03-14 06:17:19 (GMT) |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-03-27 00:00:30 (GMT) |
commit | 2a5dbead29a7c081a47133eb428440147a6d8d5a (patch) | |
tree | 75a021aeeac80fa720375a7845d27ba412d3b12f /include/linux/mtd | |
parent | 4774fb0a48aacfec206e6d54ecf58706f6a5320a (diff) | |
download | linux-fsl-qoriq-2a5dbead29a7c081a47133eb428440147a6d8d5a.tar.xz |
mtd: nand/fsmc: Remove sparse warnings and errors
This patch removes the sparse below warnings and errors for nand/fsmc driver
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
warning: incorrect type in initializer (different address spaces)
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
expected struct fsmc_regs *regs
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
got void [noderef] <asn:2>*regs_va
[...]
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'include/linux/mtd')
-rw-r--r-- | include/linux/mtd/fsmc.h | 143 |
1 files changed, 66 insertions, 77 deletions
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h index 18f9127..823359c 100644 --- a/include/linux/mtd/fsmc.h +++ b/include/linux/mtd/fsmc.h @@ -32,88 +32,77 @@ #define FSMC_FLASH_WIDTH8 1 #define FSMC_FLASH_WIDTH16 2 -struct fsmc_nor_bank_regs { - uint32_t ctrl; - uint32_t ctrl_tim; -}; - -/* ctrl register definitions */ -#define BANK_ENABLE (1 << 0) -#define MUXED (1 << 1) -#define NOR_DEV (2 << 2) -#define WIDTH_8 (0 << 4) -#define WIDTH_16 (1 << 4) -#define RSTPWRDWN (1 << 6) -#define WPROT (1 << 7) -#define WRT_ENABLE (1 << 12) -#define WAIT_ENB (1 << 13) - -/* ctrl_tim register definitions */ - -struct fsmc_nand_bank_regs { - uint32_t pc; - uint32_t sts; - uint32_t comm; - uint32_t attrib; - uint32_t ioata; - uint32_t ecc1; - uint32_t ecc2; - uint32_t ecc3; -}; - +/* fsmc controller registers for NOR flash */ +#define CTRL 0x0 + /* ctrl register definitions */ + #define BANK_ENABLE (1 << 0) + #define MUXED (1 << 1) + #define NOR_DEV (2 << 2) + #define WIDTH_8 (0 << 4) + #define WIDTH_16 (1 << 4) + #define RSTPWRDWN (1 << 6) + #define WPROT (1 << 7) + #define WRT_ENABLE (1 << 12) + #define WAIT_ENB (1 << 13) + +#define CTRL_TIM 0x4 + /* ctrl_tim register definitions */ + +#define FSMC_NOR_BANK_SZ 0x8 #define FSMC_NOR_REG_SIZE 0x40 -struct fsmc_regs { - struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS]; - uint8_t reserved_1[0x40 - 0x20]; - struct fsmc_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS]; - uint8_t reserved_2[0xfe0 - 0xc0]; - uint32_t peripid0; /* 0xfe0 */ - uint32_t peripid1; /* 0xfe4 */ - uint32_t peripid2; /* 0xfe8 */ - uint32_t peripid3; /* 0xfec */ - uint32_t pcellid0; /* 0xff0 */ - uint32_t pcellid1; /* 0xff4 */ - uint32_t pcellid2; /* 0xff8 */ - uint32_t pcellid3; /* 0xffc */ -}; +#define FSMC_NOR_REG(base, bank, reg) (base + \ + FSMC_NOR_BANK_SZ * (bank) + \ + reg) + +/* fsmc controller registers for NAND flash */ +#define PC 0x00 + /* pc register definitions */ + #define FSMC_RESET (1 << 0) + #define FSMC_WAITON (1 << 1) + #define FSMC_ENABLE (1 << 2) + #define FSMC_DEVTYPE_NAND (1 << 3) + #define FSMC_DEVWID_8 (0 << 4) + #define FSMC_DEVWID_16 (1 << 4) + #define FSMC_ECCEN (1 << 6) + #define FSMC_ECCPLEN_512 (0 << 7) + #define FSMC_ECCPLEN_256 (1 << 7) + #define FSMC_TCLR_1 (1) + #define FSMC_TCLR_SHIFT (9) + #define FSMC_TCLR_MASK (0xF) + #define FSMC_TAR_1 (1) + #define FSMC_TAR_SHIFT (13) + #define FSMC_TAR_MASK (0xF) +#define STS 0x04 + /* sts register definitions */ + #define FSMC_CODE_RDY (1 << 15) +#define COMM 0x08 + /* comm register definitions */ + #define FSMC_TSET_0 0 + #define FSMC_TSET_SHIFT 0 + #define FSMC_TSET_MASK 0xFF + #define FSMC_TWAIT_6 6 + #define FSMC_TWAIT_SHIFT 8 + #define FSMC_TWAIT_MASK 0xFF + #define FSMC_THOLD_4 4 + #define FSMC_THOLD_SHIFT 16 + #define FSMC_THOLD_MASK 0xFF + #define FSMC_THIZ_1 1 + #define FSMC_THIZ_SHIFT 24 + #define FSMC_THIZ_MASK 0xFF +#define ATTRIB 0x0C +#define IOATA 0x10 +#define ECC1 0x14 +#define ECC2 0x18 +#define ECC3 0x1C +#define FSMC_NAND_BANK_SZ 0x20 + +#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \ + (FSMC_NAND_BANK_SZ * (bank)) + \ + reg) #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) -/* pc register definitions */ -#define FSMC_RESET (1 << 0) -#define FSMC_WAITON (1 << 1) -#define FSMC_ENABLE (1 << 2) -#define FSMC_DEVTYPE_NAND (1 << 3) -#define FSMC_DEVWID_8 (0 << 4) -#define FSMC_DEVWID_16 (1 << 4) -#define FSMC_ECCEN (1 << 6) -#define FSMC_ECCPLEN_512 (0 << 7) -#define FSMC_ECCPLEN_256 (1 << 7) -#define FSMC_TCLR_1 (1) -#define FSMC_TCLR_SHIFT (9) -#define FSMC_TCLR_MASK (0xF) -#define FSMC_TAR_1 (1) -#define FSMC_TAR_SHIFT (13) -#define FSMC_TAR_MASK (0xF) - -/* sts register definitions */ -#define FSMC_CODE_RDY (1 << 15) - -/* comm register definitions */ -#define FSMC_TSET_0 0 -#define FSMC_TSET_SHIFT 0 -#define FSMC_TSET_MASK 0xFF -#define FSMC_TWAIT_6 6 -#define FSMC_TWAIT_SHIFT 8 -#define FSMC_TWAIT_MASK 0xFF -#define FSMC_THOLD_4 4 -#define FSMC_THOLD_SHIFT 16 -#define FSMC_THOLD_MASK 0xFF -#define FSMC_THIZ_1 1 -#define FSMC_THIZ_SHIFT 24 -#define FSMC_THIZ_MASK 0xFF - /* * There are 13 bytes of ecc for every 512 byte block in FSMC version 8 * and it has to be read consecutively and immediately after the 512 |