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author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-10-28 21:50:49 (GMT) |
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committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-11-08 11:29:48 (GMT) |
commit | f8beab2bb611d735767871e0e1a12dc6a0def7b1 (patch) | |
tree | a30103e40ae9d4473025edad6a2b3a28e3133fb5 /include/linux/regmap.h | |
parent | 1ea6b8f48918282bdca0b32a34095504ee65bab5 (diff) | |
download | linux-fsl-qoriq-f8beab2bb611d735767871e0e1a12dc6a0def7b1.tar.xz |
regmap: Add a reusable irq_chip for regmap based interrupt controllers
There seem to be lots of regmap-using devices with very similar interrupt
controllers with a small bank of interrupt registers and mask registers
with an interrupt per bit. This won't cover everything but it's a good
start.
Each chip supplies a base for the status registers, a base for the mask
registers, an optional base for writing acknowledgements (which may be the
same as the status registers) and an array of bits within each of these
register banks which indicate the interrupt.
There is an assumption that the bit for each interrupt will be the same
in each of the register bank.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'include/linux/regmap.h')
-rw-r--r-- | include/linux/regmap.h | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 690276a..bd54cec 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -144,4 +144,51 @@ int regcache_sync(struct regmap *map); void regcache_cache_only(struct regmap *map, bool enable); void regcache_cache_bypass(struct regmap *map, bool enable); +/** + * Description of an IRQ for the generic regmap irq_chip. + * + * @reg_offset: Offset of the status/mask register within the bank + * @mask: Mask used to flag/control the register. + */ +struct regmap_irq { + unsigned int reg_offset; + unsigned int mask; +}; + +/** + * Description of a generic regmap irq_chip. This is not intended to + * handle every possible interrupt controller, but it should handle a + * substantial proportion of those that are found in the wild. + * + * @name: Descriptive name for IRQ controller. + * + * @status_base: Base status register address. + * @mask_base: Base mask register address. + * @ack_base: Base ack address. If zero then the chip is clear on read. + * + * @num_regs: Number of registers in each control bank. + * @irqs: Descriptors for individual IRQs. Interrupt numbers are + * assigned based on the index in the array of the interrupt. + * @num_irqs: Number of descriptors. + */ +struct regmap_irq_chip { + const char *name; + + unsigned int status_base; + unsigned int mask_base; + unsigned int ack_base; + + int num_regs; + + const struct regmap_irq *irqs; + int num_irqs; +}; + +struct regmap_irq_chip_data; + +int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, + int irq_base, struct regmap_irq_chip *chip, + struct regmap_irq_chip_data **data); +void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *data); + #endif |