diff options
| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2014-03-24 10:55:10 (GMT) |
|---|---|---|
| committer | Jose Rivera <German.Rivera@freescale.com> | 2014-03-25 17:05:48 (GMT) |
| commit | 2bd36cbf3554ccf06dab56ec0249837ecab7356f (patch) | |
| tree | 7b2709e36871da92f653bf291ef32e19f64304a6 /include/uapi | |
| parent | 3be02f7adc1646d12e1d95c7036209e74b9e9ccb (diff) | |
| download | linux-fsl-qoriq-2bd36cbf3554ccf06dab56ec0249837ecab7356f.tar.xz | |
Add 64byte FiFo mode UART support for FSL platforms
T1040 FSL SoC has new version of UART controller which
can support 64byte FiFo. Add suuport to enable 64byte FiFO mode
-FCR[EN64] needs to be programmed to 1 to enable it.
-Also, when FCR[EN64]==1, RTL bits to be used as below
to define various Receive Trigger Levels:
-FCR[RTL] = 00 1 byte
-FCR[RTL] = 01 16 bytes
-FCR[RTL] = 10 32 bytes
-FCR[RTL] = 11 56 bytes
-tx_loadsz is set tp 32bytes, As some issues are observed with
64-byte mode which looks to be Si issue.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Change-Id: I0b32f3230bd1c9674a2e85cc4e5a16869dbaa9af
Reviewed-on: http://git.am.freescale.net:8181/10215
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/linux/serial_core.h | 3 | ||||
| -rw-r--r-- | include/uapi/linux/serial_reg.h | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index b47dba2..f04d8a4 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -54,7 +54,8 @@ #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */ #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */ #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */ -#define PORT_MAX_8250 28 /* max port ID */ +#define PORT_16550A_FSL64 29 /* Freescale 16550 UART with 64 FIFOs */ +#define PORT_MAX_8250 30 /* max port ID */ /* * ARM specific type numbers. These are not currently guaranteed diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h index e632260..c1ff1e7 100644 --- a/include/uapi/linux/serial_reg.h +++ b/include/uapi/linux/serial_reg.h @@ -86,7 +86,8 @@ #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ -#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */ +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750 and + some Freescale UARTs) */ #define UART_LCR 3 /* Out: Line Control Register */ /* |