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author | Olof Johansson <olof@lixom.net> | 2013-06-08 00:01:42 (GMT) |
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committer | Olof Johansson <olof@lixom.net> | 2013-06-08 01:21:51 (GMT) |
commit | e56c60c374bbcd343ed286c713116056bf3d6d36 (patch) | |
tree | 287370ef948fbd7b9dc45c54e7ed7d384258dd26 /kernel/sysctl.c | |
parent | f49024926236068bc3fe6848aaf87b914049013a (diff) | |
parent | 97c4e87d45498fb4d18c995721bba72345a7d257 (diff) | |
download | linux-fsl-qoriq-e56c60c374bbcd343ed286c713116056bf3d6d36.tar.xz |
Merge tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx into next/soc
From Michal Simek:
arm: Xilinx Zynq clock changes for v3.11
Change Xilinx Zynq DT clock description which reflects logical abstraction
of Zynq's clock tree.
- Refactor PLL driver
- Use new clock controller driver
- Change timer and uart drivers
* tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx:
clk: zynq: Remove deprecated clock code
arm: zynq: Migrate platform to clock controller
clk: zynq: Add clock controller driver
clk: zynq: Factor out PLL driver
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'kernel/sysctl.c')
0 files changed, 0 insertions, 0 deletions