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-rw-r--r--drivers/clocksource/Kconfig1
-rw-r--r--drivers/clocksource/samsung_pwm_timer.c19
2 files changed, 15 insertions, 5 deletions
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index b7b9b04..41c6946 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -99,7 +99,6 @@ config CLKSRC_EXYNOS_MCT
config CLKSRC_SAMSUNG_PWM
bool
- select CLKSRC_MMIO
help
This is a new clocksource driver for the PWM timer found in
Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver
diff --git a/drivers/clocksource/samsung_pwm_timer.c b/drivers/clocksource/samsung_pwm_timer.c
index 0c005f4..b3112dc 100644
--- a/drivers/clocksource/samsung_pwm_timer.c
+++ b/drivers/clocksource/samsung_pwm_timer.c
@@ -298,6 +298,18 @@ static void __init samsung_clockevent_init(void)
}
}
+static cycle_t samsung_clocksource_read(struct clocksource *c)
+{
+ return ~readl_relaxed(pwm.source_reg);
+}
+
+static struct clocksource samsung_clocksource = {
+ .name = "samsung_clocksource_timer",
+ .rating = 250,
+ .read = samsung_clocksource_read,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
/*
* Override the global weak sched_clock symbol with this
* local implementation which uses the clocksource to get some
@@ -307,7 +319,7 @@ static void __init samsung_clockevent_init(void)
*/
static u32 notrace samsung_read_sched_clock(void)
{
- return ~__raw_readl(pwm.source_reg);
+ return samsung_clocksource_read(NULL);
}
static void __init samsung_clocksource_init(void)
@@ -334,9 +346,8 @@ static void __init samsung_clocksource_init(void)
setup_sched_clock(samsung_read_sched_clock,
pwm.variant.bits, clock_rate);
- ret = clocksource_mmio_init(pwm.source_reg, "samsung_clocksource_timer",
- clock_rate, 250, pwm.variant.bits,
- clocksource_mmio_readl_down);
+ samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
+ ret = clocksource_register_hz(&samsung_clocksource, clock_rate);
if (ret)
panic("samsung_clocksource_timer: can't register clocksource\n");
}