diff options
Diffstat (limited to 'arch/arm/mach-omap2/devices.c')
| -rw-r--r-- | arch/arm/mach-omap2/devices.c | 394 |
1 files changed, 345 insertions, 49 deletions
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 2ee954a..9d7216f 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -14,59 +14,19 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/clk.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/map.h> +#include <mach/control.h> #include <mach/tc.h> #include <mach/board.h> #include <mach/mux.h> #include <mach/gpio.h> - -#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) - -#define OMAP2_I2C_BASE2 0x48072000 -#define OMAP2_I2C_INT2 57 - -static struct resource i2c_resources2[] = { - { - .start = OMAP2_I2C_BASE2, - .end = OMAP2_I2C_BASE2 + 0x3f, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP2_I2C_INT2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device omap_i2c_device2 = { - .name = "i2c_omap", - .id = 2, - .num_resources = ARRAY_SIZE(i2c_resources2), - .resource = i2c_resources2, -}; - -/* See also arch/arm/plat-omap/devices.c for first I2C on 24xx */ -static void omap_init_i2c(void) -{ - /* REVISIT: Second I2C not in use on H4? */ - if (machine_is_omap_h4()) - return; - - if (!cpu_is_omap2430()) { - omap_cfg_reg(J15_24XX_I2C2_SCL); - omap_cfg_reg(H19_24XX_I2C2_SDA); - } - (void) platform_device_register(&omap_i2c_device2); -} - -#else - -static void omap_init_i2c(void) {} - -#endif +#include <mach/eac.h> +#include <mach/mmc.h> #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) #define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE) @@ -104,7 +64,9 @@ static inline void omap_init_mbox(void) { } #if defined(CONFIG_OMAP_STI) -#define OMAP2_STI_BASE IO_ADDRESS(0x48068000) +#if defined(CONFIG_ARCH_OMAP2) + +#define OMAP2_STI_BASE 0x48068000 #define OMAP2_STI_CHANNEL_BASE 0x54000000 #define OMAP2_STI_IRQ 4 @@ -124,6 +86,25 @@ static struct resource sti_resources[] = { .flags = IORESOURCE_IRQ, } }; +#elif defined(CONFIG_ARCH_OMAP3) + +#define OMAP3_SDTI_BASE 0x54500000 +#define OMAP3_SDTI_CHANNEL_BASE 0x54600000 + +static struct resource sti_resources[] = { + { + .start = OMAP3_SDTI_BASE, + .end = OMAP3_SDTI_BASE + 0xFFF, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP3_SDTI_CHANNEL_BASE, + .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1, + .flags = IORESOURCE_MEM, + } +}; + +#endif static struct platform_device sti_device = { .name = "sti", @@ -140,12 +121,14 @@ static inline void omap_init_sti(void) static inline void omap_init_sti(void) {} #endif -#if defined(CONFIG_SPI_OMAP24XX) +#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) #include <mach/mcspi.h> #define OMAP2_MCSPI1_BASE 0x48098000 #define OMAP2_MCSPI2_BASE 0x4809a000 +#define OMAP2_MCSPI3_BASE 0x480b8000 +#define OMAP2_MCSPI4_BASE 0x480ba000 static struct omap2_mcspi_platform_config omap2_mcspi1_config = { .num_cs = 4, @@ -159,7 +142,7 @@ static struct resource omap2_mcspi1_resources[] = { }, }; -struct platform_device omap2_mcspi1 = { +static struct platform_device omap2_mcspi1 = { .name = "omap2_mcspi", .id = 1, .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), @@ -181,7 +164,7 @@ static struct resource omap2_mcspi2_resources[] = { }, }; -struct platform_device omap2_mcspi2 = { +static struct platform_device omap2_mcspi2 = { .name = "omap2_mcspi", .id = 2, .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), @@ -191,16 +174,327 @@ struct platform_device omap2_mcspi2 = { }, }; +#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) +static struct omap2_mcspi_platform_config omap2_mcspi3_config = { + .num_cs = 2, +}; + +static struct resource omap2_mcspi3_resources[] = { + { + .start = OMAP2_MCSPI3_BASE, + .end = OMAP2_MCSPI3_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device omap2_mcspi3 = { + .name = "omap2_mcspi", + .id = 3, + .num_resources = ARRAY_SIZE(omap2_mcspi3_resources), + .resource = omap2_mcspi3_resources, + .dev = { + .platform_data = &omap2_mcspi3_config, + }, +}; +#endif + +#ifdef CONFIG_ARCH_OMAP3 +static struct omap2_mcspi_platform_config omap2_mcspi4_config = { + .num_cs = 1, +}; + +static struct resource omap2_mcspi4_resources[] = { + { + .start = OMAP2_MCSPI4_BASE, + .end = OMAP2_MCSPI4_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device omap2_mcspi4 = { + .name = "omap2_mcspi", + .id = 4, + .num_resources = ARRAY_SIZE(omap2_mcspi4_resources), + .resource = omap2_mcspi4_resources, + .dev = { + .platform_data = &omap2_mcspi4_config, + }, +}; +#endif + static void omap_init_mcspi(void) { platform_device_register(&omap2_mcspi1); platform_device_register(&omap2_mcspi2); +#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) + platform_device_register(&omap2_mcspi3); +#endif +#ifdef CONFIG_ARCH_OMAP3 + platform_device_register(&omap2_mcspi4); +#endif } #else static inline void omap_init_mcspi(void) {} #endif +#ifdef CONFIG_SND_OMAP24XX_EAC + +#define OMAP2_EAC_BASE 0x48090000 + +static struct resource omap2_eac_resources[] = { + { + .start = OMAP2_EAC_BASE, + .end = OMAP2_EAC_BASE + 0x109, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device omap2_eac_device = { + .name = "omap24xx-eac", + .id = -1, + .num_resources = ARRAY_SIZE(omap2_eac_resources), + .resource = omap2_eac_resources, + .dev = { + .platform_data = NULL, + }, +}; + +void omap_init_eac(struct eac_platform_data *pdata) +{ + omap2_eac_device.dev.platform_data = pdata; + platform_device_register(&omap2_eac_device); +} + +#else +void omap_init_eac(struct eac_platform_data *pdata) {} +#endif + +#ifdef CONFIG_OMAP_SHA1_MD5 +static struct resource sha1_md5_resources[] = { + { + .start = OMAP24XX_SEC_SHA1MD5_BASE, + .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_24XX_SHA1MD5, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device sha1_md5_device = { + .name = "OMAP SHA1/MD5", + .id = -1, + .num_resources = ARRAY_SIZE(sha1_md5_resources), + .resource = sha1_md5_resources, +}; + +static void omap_init_sha1_md5(void) +{ + platform_device_register(&sha1_md5_device); +} +#else +static inline void omap_init_sha1_md5(void) { } +#endif + +/*-------------------------------------------------------------------------*/ + +#ifdef CONFIG_ARCH_OMAP3 + +#define MMCHS_SYSCONFIG 0x0010 +#define MMCHS_SYSCONFIG_SWRESET (1 << 1) +#define MMCHS_SYSSTATUS 0x0014 +#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) + +static struct platform_device dummy_pdev = { + .dev = { + .bus = &platform_bus_type, + }, +}; + +/** + * omap_hsmmc_reset() - Full reset of each HS-MMC controller + * + * Ensure that each MMC controller is fully reset. Controllers + * left in an unknown state (by bootloader) may prevent retention + * or OFF-mode. This is especially important in cases where the + * MMC driver is not enabled, _or_ built as a module. + * + * In order for reset to work, interface, functional and debounce + * clocks must be enabled. The debounce clock comes from func_32k_clk + * and is not under SW control, so we only enable i- and f-clocks. + **/ +static void __init omap_hsmmc_reset(void) +{ + u32 i, nr_controllers = cpu_is_omap34xx() ? OMAP34XX_NR_MMC : + OMAP24XX_NR_MMC; + + for (i = 0; i < nr_controllers; i++) { + u32 v, base = 0; + struct clk *iclk, *fclk; + struct device *dev = &dummy_pdev.dev; + + switch (i) { + case 0: + base = OMAP2_MMC1_BASE; + break; + case 1: + base = OMAP2_MMC2_BASE; + break; + case 2: + base = OMAP3_MMC3_BASE; + break; + } + + dummy_pdev.id = i; + iclk = clk_get(dev, "mmchs_ick"); + if (iclk && clk_enable(iclk)) + iclk = NULL; + + fclk = clk_get(dev, "mmchs_fck"); + if (fclk && clk_enable(fclk)) + fclk = NULL; + + if (!iclk || !fclk) { + printk(KERN_WARNING + "%s: Unable to enable clocks for MMC%d, " + "cannot reset.\n", __func__, i); + break; + } + + omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); + v = omap_readl(base + MMCHS_SYSSTATUS); + while (!(omap_readl(base + MMCHS_SYSSTATUS) & + MMCHS_SYSSTATUS_RESETDONE)) + cpu_relax(); + + if (fclk) { + clk_disable(fclk); + clk_put(fclk); + } + if (iclk) { + clk_disable(iclk); + clk_put(iclk); + } + } +} +#else +static inline void omap_hsmmc_reset(void) {} +#endif + +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ + defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) + +static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, + int controller_nr) +{ + if (cpu_is_omap2420() && controller_nr == 0) { + omap_cfg_reg(H18_24XX_MMC_CMD); + omap_cfg_reg(H15_24XX_MMC_CLKI); + omap_cfg_reg(G19_24XX_MMC_CLKO); + omap_cfg_reg(F20_24XX_MMC_DAT0); + omap_cfg_reg(F19_24XX_MMC_DAT_DIR0); + omap_cfg_reg(G18_24XX_MMC_CMD_DIR); + if (mmc_controller->slots[0].wires == 4) { + omap_cfg_reg(H14_24XX_MMC_DAT1); + omap_cfg_reg(E19_24XX_MMC_DAT2); + omap_cfg_reg(D19_24XX_MMC_DAT3); + omap_cfg_reg(E20_24XX_MMC_DAT_DIR1); + omap_cfg_reg(F18_24XX_MMC_DAT_DIR2); + omap_cfg_reg(E18_24XX_MMC_DAT_DIR3); + } + + /* + * Use internal loop-back in MMC/SDIO Module Input Clock + * selection + */ + if (mmc_controller->slots[0].internal_clock) { + u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + v |= (1 << 24); + omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); + } + } +} + +void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, + int nr_controllers) +{ + int i; + + for (i = 0; i < nr_controllers; i++) { + unsigned long base, size; + unsigned int irq = 0; + + if (!mmc_data[i]) + continue; + + omap2_mmc_mux(mmc_data[i], i); + + switch (i) { + case 0: + base = OMAP2_MMC1_BASE; + irq = INT_24XX_MMC_IRQ; + break; + case 1: + base = OMAP2_MMC2_BASE; + irq = INT_24XX_MMC2_IRQ; + break; + case 2: + if (!cpu_is_omap34xx()) + return; + base = OMAP3_MMC3_BASE; + irq = INT_34XX_MMC3_IRQ; + break; + default: + continue; + } + + if (cpu_is_omap2420()) + size = OMAP2420_MMC_SIZE; + else + size = HSMMC_SIZE; + + omap_mmc_add(i, base, size, irq, mmc_data[i]); + }; +} + +#endif + +/*-------------------------------------------------------------------------*/ + +#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) +#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) +#define OMAP_HDQ_BASE 0x480B2000 +#endif +static struct resource omap_hdq_resources[] = { + { + .start = OMAP_HDQ_BASE, + .end = OMAP_HDQ_BASE + 0x1C, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_24XX_HDQ_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct platform_device omap_hdq_dev = { + .name = "omap_hdq", + .id = 0, + .dev = { + .platform_data = NULL, + }, + .num_resources = ARRAY_SIZE(omap_hdq_resources), + .resource = omap_hdq_resources, +}; +static inline void omap_hdq_init(void) +{ + (void) platform_device_register(&omap_hdq_dev); +} +#else +static inline void omap_hdq_init(void) {} +#endif + /*-------------------------------------------------------------------------*/ static int __init omap2_init_devices(void) @@ -208,10 +502,12 @@ static int __init omap2_init_devices(void) /* please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ - omap_init_i2c(); + omap_hsmmc_reset(); omap_init_mbox(); omap_init_mcspi(); + omap_hdq_init(); omap_init_sti(); + omap_init_sha1_md5(); return 0; } |