diff options
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 17 |
1 files changed, 5 insertions, 12 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 371869d..c78abab 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -278,18 +278,6 @@ static struct clk_ops tegra_clk_m_ops = { .disable = tegra2_clk_m_disable, }; -void tegra2_periph_reset_assert(struct clk *c) -{ - BUG_ON(!c->ops->reset); - c->ops->reset(c, true); -} - -void tegra2_periph_reset_deassert(struct clk *c) -{ - BUG_ON(!c->ops->reset); - c->ops->reset(c, false); -} - /* super clock functions */ /* "super clocks" on tegra have two-stage muxes and a clock skipping * super divider. We will ignore the clock skipping divider, since we @@ -1132,6 +1120,9 @@ static struct clk_ops tegra_periph_clk_ops = { void tegra2_sdmmc_tap_delay(struct clk *c, int delay) { u32 reg; + unsigned long flags; + + spin_lock_irqsave(&c->spinlock, flags); delay = clamp(delay, 0, 15); reg = clk_readl(c->reg); @@ -1139,6 +1130,8 @@ void tegra2_sdmmc_tap_delay(struct clk *c, int delay) reg |= SDMMC_CLK_INT_FB_SEL; reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT; clk_writel(reg, c->reg); + + spin_unlock_irqrestore(&c->spinlock, flags); } /* External memory controller clock ops */ |