diff options
Diffstat (limited to 'arch/mips/bcm63xx/cpu.c')
-rw-r--r-- | arch/mips/bcm63xx/cpu.c | 180 |
1 files changed, 26 insertions, 154 deletions
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 7c7e4d4..8bd5133 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -29,166 +29,38 @@ static u16 bcm63xx_cpu_rev; static unsigned int bcm63xx_cpu_freq; static unsigned int bcm63xx_memory_size; -/* - * 6338 register sets and irqs - */ -static const unsigned long bcm96338_regs_base[] = { - [RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE, - [RSET_PERF] = BCM_6338_PERF_BASE, - [RSET_TIMER] = BCM_6338_TIMER_BASE, - [RSET_WDT] = BCM_6338_WDT_BASE, - [RSET_UART0] = BCM_6338_UART0_BASE, - [RSET_UART1] = BCM_6338_UART1_BASE, - [RSET_GPIO] = BCM_6338_GPIO_BASE, - [RSET_SPI] = BCM_6338_SPI_BASE, - [RSET_OHCI0] = BCM_6338_OHCI0_BASE, - [RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE, - [RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE, - [RSET_UDC0] = BCM_6338_UDC0_BASE, - [RSET_MPI] = BCM_6338_MPI_BASE, - [RSET_PCMCIA] = BCM_6338_PCMCIA_BASE, - [RSET_SDRAM] = BCM_6338_SDRAM_BASE, - [RSET_DSL] = BCM_6338_DSL_BASE, - [RSET_ENET0] = BCM_6338_ENET0_BASE, - [RSET_ENET1] = BCM_6338_ENET1_BASE, - [RSET_ENETDMA] = BCM_6338_ENETDMA_BASE, - [RSET_MEMC] = BCM_6338_MEMC_BASE, - [RSET_DDR] = BCM_6338_DDR_BASE, +static const unsigned long bcm6338_regs_base[] = { + __GEN_CPU_REGS_TABLE(6338) }; -static const int bcm96338_irqs[] = { - [IRQ_TIMER] = BCM_6338_TIMER_IRQ, - [IRQ_UART0] = BCM_6338_UART0_IRQ, - [IRQ_DSL] = BCM_6338_DSL_IRQ, - [IRQ_ENET0] = BCM_6338_ENET0_IRQ, - [IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ, - [IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ, - [IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ, +static const int bcm6338_irqs[] = { + __GEN_CPU_IRQ_TABLE(6338) }; -/* - * 6345 register sets and irqs - */ -static const unsigned long bcm96345_regs_base[] = { - [RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE, - [RSET_PERF] = BCM_6345_PERF_BASE, - [RSET_TIMER] = BCM_6345_TIMER_BASE, - [RSET_WDT] = BCM_6345_WDT_BASE, - [RSET_UART0] = BCM_6345_UART0_BASE, - [RSET_UART1] = BCM_6345_UART1_BASE, - [RSET_GPIO] = BCM_6345_GPIO_BASE, - [RSET_SPI] = BCM_6345_SPI_BASE, - [RSET_UDC0] = BCM_6345_UDC0_BASE, - [RSET_OHCI0] = BCM_6345_OHCI0_BASE, - [RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE, - [RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE, - [RSET_MPI] = BCM_6345_MPI_BASE, - [RSET_PCMCIA] = BCM_6345_PCMCIA_BASE, - [RSET_DSL] = BCM_6345_DSL_BASE, - [RSET_ENET0] = BCM_6345_ENET0_BASE, - [RSET_ENET1] = BCM_6345_ENET1_BASE, - [RSET_ENETDMA] = BCM_6345_ENETDMA_BASE, - [RSET_EHCI0] = BCM_6345_EHCI0_BASE, - [RSET_SDRAM] = BCM_6345_SDRAM_BASE, - [RSET_MEMC] = BCM_6345_MEMC_BASE, - [RSET_DDR] = BCM_6345_DDR_BASE, +static const unsigned long bcm6345_regs_base[] = { + __GEN_CPU_REGS_TABLE(6345) }; -static const int bcm96345_irqs[] = { - [IRQ_TIMER] = BCM_6345_TIMER_IRQ, - [IRQ_UART0] = BCM_6345_UART0_IRQ, - [IRQ_DSL] = BCM_6345_DSL_IRQ, - [IRQ_ENET0] = BCM_6345_ENET0_IRQ, - [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ, - [IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ, - [IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ, +static const int bcm6345_irqs[] = { + __GEN_CPU_IRQ_TABLE(6345) }; -/* - * 6348 register sets and irqs - */ -static const unsigned long bcm96348_regs_base[] = { - [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE, - [RSET_PERF] = BCM_6348_PERF_BASE, - [RSET_TIMER] = BCM_6348_TIMER_BASE, - [RSET_WDT] = BCM_6348_WDT_BASE, - [RSET_UART0] = BCM_6348_UART0_BASE, - [RSET_UART1] = BCM_6348_UART1_BASE, - [RSET_GPIO] = BCM_6348_GPIO_BASE, - [RSET_SPI] = BCM_6348_SPI_BASE, - [RSET_OHCI0] = BCM_6348_OHCI0_BASE, - [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE, - [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE, - [RSET_MPI] = BCM_6348_MPI_BASE, - [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE, - [RSET_SDRAM] = BCM_6348_SDRAM_BASE, - [RSET_DSL] = BCM_6348_DSL_BASE, - [RSET_ENET0] = BCM_6348_ENET0_BASE, - [RSET_ENET1] = BCM_6348_ENET1_BASE, - [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE, - [RSET_MEMC] = BCM_6348_MEMC_BASE, - [RSET_DDR] = BCM_6348_DDR_BASE, +static const unsigned long bcm6348_regs_base[] = { + __GEN_CPU_REGS_TABLE(6348) }; -static const int bcm96348_irqs[] = { - [IRQ_TIMER] = BCM_6348_TIMER_IRQ, - [IRQ_UART0] = BCM_6348_UART0_IRQ, - [IRQ_DSL] = BCM_6348_DSL_IRQ, - [IRQ_ENET0] = BCM_6348_ENET0_IRQ, - [IRQ_ENET1] = BCM_6348_ENET1_IRQ, - [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ, - [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ, - [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ, - [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ, - [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ, - [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ, - [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ, - [IRQ_PCI] = BCM_6348_PCI_IRQ, +static const int bcm6348_irqs[] = { + __GEN_CPU_IRQ_TABLE(6348) + }; -/* - * 6358 register sets and irqs - */ -static const unsigned long bcm96358_regs_base[] = { - [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE, - [RSET_PERF] = BCM_6358_PERF_BASE, - [RSET_TIMER] = BCM_6358_TIMER_BASE, - [RSET_WDT] = BCM_6358_WDT_BASE, - [RSET_UART0] = BCM_6358_UART0_BASE, - [RSET_UART1] = BCM_6358_UART1_BASE, - [RSET_GPIO] = BCM_6358_GPIO_BASE, - [RSET_SPI] = BCM_6358_SPI_BASE, - [RSET_OHCI0] = BCM_6358_OHCI0_BASE, - [RSET_EHCI0] = BCM_6358_EHCI0_BASE, - [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE, - [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE, - [RSET_MPI] = BCM_6358_MPI_BASE, - [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE, - [RSET_SDRAM] = BCM_6358_SDRAM_BASE, - [RSET_DSL] = BCM_6358_DSL_BASE, - [RSET_ENET0] = BCM_6358_ENET0_BASE, - [RSET_ENET1] = BCM_6358_ENET1_BASE, - [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE, - [RSET_MEMC] = BCM_6358_MEMC_BASE, - [RSET_DDR] = BCM_6358_DDR_BASE, +static const unsigned long bcm6358_regs_base[] = { + __GEN_CPU_REGS_TABLE(6358) }; -static const int bcm96358_irqs[] = { - [IRQ_TIMER] = BCM_6358_TIMER_IRQ, - [IRQ_UART0] = BCM_6358_UART0_IRQ, - [IRQ_UART1] = BCM_6358_UART1_IRQ, - [IRQ_DSL] = BCM_6358_DSL_IRQ, - [IRQ_ENET0] = BCM_6358_ENET0_IRQ, - [IRQ_ENET1] = BCM_6358_ENET1_IRQ, - [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ, - [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ, - [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ, - [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ, - [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ, - [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ, - [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ, - [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ, - [IRQ_PCI] = BCM_6358_PCI_IRQ, +static const int bcm6358_irqs[] = { + __GEN_CPU_IRQ_TABLE(6358) + }; u16 __bcm63xx_get_cpu_id(void) @@ -301,24 +173,24 @@ void __init bcm63xx_cpu_init(void) case CPU_BMIPS3300: if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) { expected_cpu_id = BCM6348_CPU_ID; - bcm63xx_regs_base = bcm96348_regs_base; - bcm63xx_irqs = bcm96348_irqs; + bcm63xx_regs_base = bcm6348_regs_base; + bcm63xx_irqs = bcm6348_irqs; } else { __cpu_name[cpu] = "Broadcom BCM6338"; expected_cpu_id = BCM6338_CPU_ID; - bcm63xx_regs_base = bcm96338_regs_base; - bcm63xx_irqs = bcm96338_irqs; + bcm63xx_regs_base = bcm6338_regs_base; + bcm63xx_irqs = bcm6338_irqs; } break; case CPU_BMIPS32: expected_cpu_id = BCM6345_CPU_ID; - bcm63xx_regs_base = bcm96345_regs_base; - bcm63xx_irqs = bcm96345_irqs; + bcm63xx_regs_base = bcm6345_regs_base; + bcm63xx_irqs = bcm6345_irqs; break; case CPU_BMIPS4350: expected_cpu_id = BCM6358_CPU_ID; - bcm63xx_regs_base = bcm96358_regs_base; - bcm63xx_irqs = bcm96358_irqs; + bcm63xx_regs_base = bcm6358_regs_base; + bcm63xx_irqs = bcm6358_irqs; break; } |