diff options
Diffstat (limited to 'arch/mips/mti-malta')
-rw-r--r-- | arch/mips/mti-malta/malta-amon.c | 7 | ||||
-rw-r--r-- | arch/mips/mti-malta/malta-int.c | 119 | ||||
-rw-r--r-- | arch/mips/mti-malta/malta-memory.c | 3 | ||||
-rw-r--r-- | arch/mips/mti-malta/malta-pci.c | 27 |
4 files changed, 102 insertions, 54 deletions
diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c index df9e526..469d9b0 100644 --- a/arch/mips/mti-malta/malta-amon.c +++ b/arch/mips/mti-malta/malta-amon.c @@ -70,11 +70,12 @@ void amon_cpu_start(int cpu, launch->sp = sp; launch->a0 = a0; - /* Make sure target sees parameters before the go bit */ - smp_mb(); - + smp_wmb(); /* Target must see parameters before go */ launch->flags |= LAUNCH_FGO; + smp_wmb(); /* Target must see go before we poll */ + while ((launch->flags & LAUNCH_FGONE) == 0) ; + smp_rmb(); /* Target will be updating flags soon */ pr_debug("launch: cpu%d gone!\n", cpu); } diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 3e0a9b3..4c3fca1 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -87,7 +87,7 @@ static inline int mips_pcibios_iack(void) dummy = BONITO_PCIMAP_CFG; iob(); /* sync */ - irq = readl((u32 *)_pcictrl_bonito_pcicfg); + irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); iob(); /* sync */ irq &= 0xff; BONITO_PCIMAP_CFG = 0; @@ -379,38 +379,43 @@ static msc_irqmap_t __initdata msc_eicirqmap[] = { static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); -#if defined(CONFIG_MIPS_MT_SMP) /* * This GIC specific tabular array defines the association between External * Interrupts and CPUs/Core Interrupts. The nature of the External * Interrupts is also defined here - polarity/trigger. */ + +#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { - { GIC_EXT_INTR(0), X, X, X, X, 0 }, - { GIC_EXT_INTR(1), X, X, X, X, 0 }, - { GIC_EXT_INTR(2), X, X, X, X, 0 }, - { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(10), X, X, X, X, 0 }, - { GIC_EXT_INTR(11), X, X, X, X, 0 }, - { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(15), X, X, X, X, 0 }, -/* This is the end of the general interrupts now we do IPI ones */ + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { X, X, X, X, 0 }, + /* The remainder of this table is initialised by fill_ipi_map */ }; -#endif /* * GCMP needs to be detected before any SMP initialisation */ int __init gcmp_probe(unsigned long addr, unsigned long size) { + if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) { + gcmp_present = 0; + return gcmp_present; + } + if (gcmp_present >= 0) return gcmp_present; @@ -419,20 +424,35 @@ int __init gcmp_probe(unsigned long addr, unsigned long size) gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; if (gcmp_present) - printk(KERN_DEBUG "GCMP present\n"); + pr_debug("GCMP present\n"); return gcmp_present; } +/* Return the number of IOCU's present */ +int __init gcmp_niocu(void) +{ + return gcmp_present ? + (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF : + 0; +} + +/* Set GCMP region attributes */ +void __init gcmp_setregion(int region, unsigned long base, + unsigned long mask, int type) +{ + GCMPGCBn(CMxBASE, region) = base; + GCMPGCBn(CMxMASK, region) = mask | type; +} + #if defined(CONFIG_MIPS_MT_SMP) static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) { int intr = baseintr + cpu; - gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr); gic_intr_map[intr].cpunum = cpu; gic_intr_map[intr].pin = cpupin; gic_intr_map[intr].polarity = GIC_POL_POS; gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; - gic_intr_map[intr].ipiflag = 1; + gic_intr_map[intr].flags = GIC_FLAG_IPI; ipi_map[cpu] |= (1 << (cpupin + 2)); } @@ -447,6 +467,12 @@ static void __init fill_ipi_map(void) } #endif +void __init arch_init_ipiirq(int irq, struct irqaction *action) +{ + setup_irq(irq, action); + set_irq_handler(irq, handle_percpu_irq); +} + void __init arch_init_irq(void) { init_i8259_irqs(); @@ -458,12 +484,17 @@ void __init arch_init_irq(void) GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; gic_present = 1; } else { - _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); - gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & - MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; + if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { + _msc01_biu_base = (unsigned long) + ioremap_nocache(MSC01_BIU_REG_BASE, + MSC01_BIU_ADDRSPACE_SZ); + gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & + MSC01_SC_CFG_GICPRES_MSK) >> + MSC01_SC_CFG_GICPRES_SHF; + } } if (gic_present) - printk(KERN_DEBUG "GIC present\n"); + pr_debug("GIC present\n"); switch (mips_revision_sconid) { case MIPS_REVISION_SCON_SOCIT: @@ -526,16 +557,16 @@ void __init arch_init_irq(void) &corehi_irqaction); } -#if defined(CONFIG_MIPS_MT_SMP) if (gic_present) { /* FIXME */ int i; - +#if defined(CONFIG_MIPS_MT_SMP) gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; gic_resched_int_base = gic_call_int_base - NR_CPUS; - fill_ipi_map(); - gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); +#endif + gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); if (!gcmp_present) { /* Enable the GIC */ i = REG(_msc01_biu_base, MSC01_SC_CFG); @@ -543,7 +574,7 @@ void __init arch_init_irq(void) (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); pr_debug("GIC Enabled\n"); } - +#if defined(CONFIG_MIPS_MT_SMP) /* set up ipi interrupts */ if (cpu_has_vint) { set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); @@ -556,16 +587,14 @@ void __init arch_init_irq(void) write_c0_status(0x1100dc00); printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); for (i = 0; i < NR_CPUS; i++) { - setup_irq(MIPS_GIC_IRQ_BASE + - GIC_RESCHED_INT(i), &irq_resched); - setup_irq(MIPS_GIC_IRQ_BASE + - GIC_CALL_INT(i), &irq_call); - set_irq_handler(MIPS_GIC_IRQ_BASE + - GIC_RESCHED_INT(i), handle_percpu_irq); - set_irq_handler(MIPS_GIC_IRQ_BASE + - GIC_CALL_INT(i), handle_percpu_irq); + arch_init_ipiirq(MIPS_GIC_IRQ_BASE + + GIC_RESCHED_INT(i), &irq_resched); + arch_init_ipiirq(MIPS_GIC_IRQ_BASE + + GIC_CALL_INT(i), &irq_call); } +#endif } else { +#if defined(CONFIG_MIPS_MT_SMP) /* set up ipi interrupts */ if (cpu_has_veic) { set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); @@ -580,14 +609,10 @@ void __init arch_init_irq(void) cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; } - - setup_irq(cpu_ipi_resched_irq, &irq_resched); - setup_irq(cpu_ipi_call_irq, &irq_call); - - set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); - set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); - } + arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); + arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); #endif + } } void malta_be_init(void) diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index 61888ff..9035c64 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -54,7 +54,8 @@ static struct prom_pmemblock * __init prom_getmdesc(void) { char *memsize_str; unsigned int memsize; - char cmdline[CL_SIZE], *ptr; + char *ptr; + static char cmdline[CL_SIZE] __initdata; /* otherwise look in the environment */ memsize_str = prom_getenv("memsize"); diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index b974319..2fbfa1a 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c @@ -27,7 +27,7 @@ #include <linux/init.h> #include <asm/gt64120.h> - +#include <asm/gcmpregs.h> #include <asm/mips-boards/generic.h> #include <asm/mips-boards/bonito64.h> #include <asm/mips-boards/msc01_pci.h> @@ -201,7 +201,11 @@ void __init mips_pcibios_init(void) msc_mem_resource.start = start & mask; msc_mem_resource.end = (start & mask) | ~mask; msc_controller.mem_offset = (start & mask) - (map & mask); - +#ifdef CONFIG_MIPS_CMP + if (gcmp_niocu()) + gcmp_setregion(0, start, mask, + GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); +#endif MSC_READ(MSC01_PCI_SC2PIOBASL, start); MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); MSC_READ(MSC01_PCI_SC2PIOMAPL, map); @@ -209,7 +213,11 @@ void __init mips_pcibios_init(void) msc_io_resource.end = (map & mask) | ~mask; msc_controller.io_offset = 0; ioport_resource.end = ~mask; - +#ifdef CONFIG_MIPS_CMP + if (gcmp_niocu()) + gcmp_setregion(1, start, mask, + GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); +#endif /* If ranges overlap I/O takes precedence. */ start = start & mask; end = start | ~mask; @@ -241,3 +249,16 @@ void __init mips_pcibios_init(void) register_pci_controller(controller); } + +/* Enable PCI 2.1 compatibility in PIIX4 */ +static void __init quirk_dlcsetup(struct pci_dev *dev) +{ + u8 odlc, ndlc; + (void) pci_read_config_byte(dev, 0x82, &odlc); + /* Enable passive releases and delayed transaction */ + ndlc = odlc | 7; + (void) pci_write_config_byte(dev, 0x82, ndlc); +} + +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, + quirk_dlcsetup); |