diff options
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi index 7b4426e..ee7263b 100644 --- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi @@ -34,6 +34,8 @@ /dts-v1/; +/include/ "e6500_power_isa.dtsi" + / { compatible = "fsl,B4420"; #address-cells = <2>; @@ -48,7 +50,18 @@ serial1 = &serial1; serial2 = &serial2; serial3 = &serial3; + + crypto = &crypto; + qman = &qman; + bman = &bman; + fman0 = &fman0; + ethernet0 = &fm1mac1; + ethernet1 = &fm1mac2; + ethernet2 = &fm1mac3; + ethernet3 = &fm1mac4; + pci0 = &pci0; + usb0 = &usb0; dma0 = &dma0; dma1 = &dma1; sdhc = &sdhc; @@ -59,15 +72,45 @@ #address-cells = <1>; #size-cells = <0>; + /* + * Temporarily add next-level-cache info in each cpu node so + * that uboot can do L2 cache fixup. This can be removed once + * u-boot can create cpu node with cache info. + */ cpu0: PowerPC,e6500@0 { device_type = "cpu"; reg = <0 1>; + clocks = <&mux0>; next-level-cache = <&L2>; }; cpu1: PowerPC,e6500@2 { device_type = "cpu"; reg = <2 3>; + clocks = <&mux0>; next-level-cache = <&L2>; }; }; + + dsp-clusters { + #address-cells = <1>; + #size-cells = <0>; + + dsp-cluster0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,sc3900-cluster"; + reg = <0>; + + dsp0: dsp@0 { + compatible = "fsl,sc3900"; + reg = <0>; + next-level-cache = <&L2_2>; + }; + dsp1: dsp@1 { + compatible = "fsl,sc3900"; + reg = <1>; + next-level-cache = <&L2_2>; + }; + }; + }; }; |