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/*
 * B4420 Silicon/SoC Device Tree Source (pre include)
 *
 * Copyright 2012 Freescale Semiconductor, Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * This software is provided by Freescale Semiconductor "as is" and any
 * express or implied warranties, including, but not limited to, the implied
 * warranties of merchantability and fitness for a particular purpose are
 * disclaimed. In no event shall Freescale Semiconductor be liable for any
 * direct, indirect, incidental, special, exemplary, or consequential damages
 * (including, but not limited to, procurement of substitute goods or services;
 * loss of use, data, or profits; or business interruption) however caused and
 * on any theory of liability, whether in contract, strict liability, or tort
 * (including negligence or otherwise) arising in any way out of the use of
 * this software, even if advised of the possibility of such damage.
 */

/dts-v1/;

/include/ "e6500_power_isa.dtsi"

/ {
	compatible = "fsl,B4420";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	aliases {
		ccsr = &soc;
		dcsr = &dcsr;

		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serial3;

		crypto = &crypto;
		qman = &qman;
		bman = &bman;
		fman0 = &fman0;
		ethernet0 = &fm1mac1;
		ethernet1 = &fm1mac2;
		ethernet2 = &fm1mac3;
		ethernet3 = &fm1mac4;

		pci0 = &pci0;
		usb0 = &usb0;
		dma0 = &dma0;
		dma1 = &dma1;
		sdhc = &sdhc;
	};


	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		/*
		 * Temporarily add next-level-cache info in each cpu node so
		 * that uboot can do L2 cache fixup. This can be removed once
		 * u-boot can create cpu node with cache info.
		 */
		cpu0: PowerPC,e6500@0 {
			device_type = "cpu";
			reg = <0 1>;
			clocks = <&mux0>;
			next-level-cache = <&L2>;
		};
		cpu1: PowerPC,e6500@2 {
			device_type = "cpu";
			reg = <2 3>;
			clocks = <&mux0>;
			next-level-cache = <&L2>;
		};
	};

	dsp-clusters {
		#address-cells = <1>;
		#size-cells = <0>;

		dsp-cluster0 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,sc3900-cluster";
			reg = <0>;

			dsp0: dsp@0 {
				compatible = "fsl,sc3900";
				reg = <0>;
				next-level-cache = <&L2_2>;
			};
			dsp1: dsp@1 {
				compatible = "fsl,sc3900";
				reg = <1>;
				next-level-cache = <&L2_2>;
			};
		};
	};
};