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path: root/drivers/ata/sata_vsc.c
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Diffstat (limited to 'drivers/ata/sata_vsc.c')
-rw-r--r--drivers/ata/sata_vsc.c80
1 files changed, 40 insertions, 40 deletions
diff --git a/drivers/ata/sata_vsc.c b/drivers/ata/sata_vsc.c
index af77f71..7596e9a 100644
--- a/drivers/ata/sata_vsc.c
+++ b/drivers/ata/sata_vsc.c
@@ -50,6 +50,8 @@
#define DRV_VERSION "2.0"
enum {
+ VSC_MMIO_BAR = 0,
+
/* Interrupt register offsets (from chip base address) */
VSC_SATA_INT_STAT_OFFSET = 0x00,
VSC_SATA_INT_MASK_OFFSET = 0x04,
@@ -104,7 +106,7 @@ static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
if (sc_reg > SCR_CONTROL)
return 0xffffffffU;
- return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
+ return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
}
@@ -113,7 +115,7 @@ static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
{
if (sc_reg > SCR_CONTROL)
return;
- writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
+ writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
}
@@ -122,7 +124,7 @@ static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
void __iomem *mask_addr;
u8 mask;
- mask_addr = ap->host->mmio_base +
+ mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
VSC_SATA_INT_MASK_OFFSET + ap->port_no;
mask = readb(mask_addr);
if (ctl & ATA_NIEN)
@@ -149,25 +151,25 @@ static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
}
if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
writew(tf->feature | (((u16)tf->hob_feature) << 8),
- (void __iomem *) ioaddr->feature_addr);
+ ioaddr->feature_addr);
writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
- (void __iomem *) ioaddr->nsect_addr);
+ ioaddr->nsect_addr);
writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
- (void __iomem *) ioaddr->lbal_addr);
+ ioaddr->lbal_addr);
writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
- (void __iomem *) ioaddr->lbam_addr);
+ ioaddr->lbam_addr);
writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
- (void __iomem *) ioaddr->lbah_addr);
+ ioaddr->lbah_addr);
} else if (is_addr) {
- writew(tf->feature, (void __iomem *) ioaddr->feature_addr);
- writew(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
- writew(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
- writew(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
- writew(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
+ writew(tf->feature, ioaddr->feature_addr);
+ writew(tf->nsect, ioaddr->nsect_addr);
+ writew(tf->lbal, ioaddr->lbal_addr);
+ writew(tf->lbam, ioaddr->lbam_addr);
+ writew(tf->lbah, ioaddr->lbah_addr);
}
if (tf->flags & ATA_TFLAG_DEVICE)
- writeb(tf->device, (void __iomem *) ioaddr->device_addr);
+ writeb(tf->device, ioaddr->device_addr);
ata_wait_idle(ap);
}
@@ -179,12 +181,12 @@ static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
u16 nsect, lbal, lbam, lbah, feature;
tf->command = ata_check_status(ap);
- tf->device = readw((void __iomem *) ioaddr->device_addr);
- feature = readw((void __iomem *) ioaddr->error_addr);
- nsect = readw((void __iomem *) ioaddr->nsect_addr);
- lbal = readw((void __iomem *) ioaddr->lbal_addr);
- lbam = readw((void __iomem *) ioaddr->lbam_addr);
- lbah = readw((void __iomem *) ioaddr->lbah_addr);
+ tf->device = readw(ioaddr->device_addr);
+ feature = readw(ioaddr->error_addr);
+ nsect = readw(ioaddr->nsect_addr);
+ lbal = readw(ioaddr->lbal_addr);
+ lbam = readw(ioaddr->lbam_addr);
+ lbah = readw(ioaddr->lbah_addr);
tf->feature = feature;
tf->nsect = nsect;
@@ -216,7 +218,8 @@ static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
spin_lock(&host->lock);
- int_status = readl(host->mmio_base + VSC_SATA_INT_STAT_OFFSET);
+ int_status = readl(host->iomap[VSC_MMIO_BAR] +
+ VSC_SATA_INT_STAT_OFFSET);
for (i = 0; i < host->n_ports; i++) {
if (int_status & ((u32) 0xFF << (8 * i))) {
@@ -300,7 +303,7 @@ static const struct ata_port_operations vsc_sata_ops = {
.bmdma_status = ata_bmdma_status,
.qc_prep = ata_qc_prep,
.qc_issue = ata_qc_issue_prot,
- .data_xfer = ata_mmio_data_xfer,
+ .data_xfer = ata_data_xfer,
.freeze = ata_bmdma_freeze,
.thaw = ata_bmdma_thaw,
.error_handler = ata_bmdma_error_handler,
@@ -312,7 +315,8 @@ static const struct ata_port_operations vsc_sata_ops = {
.port_start = ata_port_start,
};
-static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
+static void __devinit vsc_sata_setup_port(struct ata_ioports *port,
+ void __iomem *base)
{
port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
@@ -329,16 +333,15 @@ static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned lon
port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
- writel(0, (void __iomem *) base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
- writel(0, (void __iomem *) base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
+ writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
+ writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
}
static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
static int printed_version;
- struct ata_probe_ent *probe_ent = NULL;
- unsigned long base;
+ struct ata_probe_ent *probe_ent;
void __iomem *mmio_base;
int rc;
@@ -355,11 +358,11 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d
if (pci_resource_len(pdev, 0) == 0)
return -ENODEV;
- rc = pci_request_regions(pdev, DRV_NAME);
- if (rc) {
+ rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
+ if (rc == -EBUSY)
pcim_pin_device(pdev);
+ if (rc)
return rc;
- }
/*
* Use 32 bit DMA mask, because 64 bit address support is poor.
@@ -377,11 +380,6 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d
probe_ent->dev = pci_dev_to_dev(pdev);
INIT_LIST_HEAD(&probe_ent->node);
- mmio_base = pcim_iomap(pdev, 0, 0);
- if (mmio_base == NULL)
- return -ENOMEM;
- base = (unsigned long) mmio_base;
-
/*
* Due to a bug in the chip, the default cache line size can't be used
*/
@@ -398,7 +396,7 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d
probe_ent->port_ops = &vsc_sata_ops;
probe_ent->n_ports = 4;
probe_ent->irq = pdev->irq;
- probe_ent->mmio_base = mmio_base;
+ probe_ent->iomap = pcim_iomap_table(pdev);
/* We don't care much about the PIO/UDMA masks, but the core won't like us
* if we don't fill these
@@ -407,11 +405,13 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d
probe_ent->mwdma_mask = 0x07;
probe_ent->udma_mask = 0x7f;
+ mmio_base = probe_ent->iomap[VSC_MMIO_BAR];
+
/* We have 4 ports per PCI function */
- vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
- vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
- vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
- vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
+ vsc_sata_setup_port(&probe_ent->port[0], mmio_base + 1 * VSC_SATA_PORT_OFFSET);
+ vsc_sata_setup_port(&probe_ent->port[1], mmio_base + 2 * VSC_SATA_PORT_OFFSET);
+ vsc_sata_setup_port(&probe_ent->port[2], mmio_base + 3 * VSC_SATA_PORT_OFFSET);
+ vsc_sata_setup_port(&probe_ent->port[3], mmio_base + 4 * VSC_SATA_PORT_OFFSET);
pci_set_master(pdev);
generated by cgit v0.10.2 at 2024-11-21 09:28:20 (GMT)