diff options
Diffstat (limited to 'drivers/gpu/drm/gma500/intel_gmbus.c')
-rw-r--r-- | drivers/gpu/drm/gma500/intel_gmbus.c | 90 |
1 files changed, 41 insertions, 49 deletions
diff --git a/drivers/gpu/drm/gma500/intel_gmbus.c b/drivers/gpu/drm/gma500/intel_gmbus.c index 566d330..62cd42e 100644 --- a/drivers/gpu/drm/gma500/intel_gmbus.c +++ b/drivers/gpu/drm/gma500/intel_gmbus.c @@ -51,9 +51,6 @@ #define wait_for(COND, MS) _wait_for(COND, MS, 1) #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) -#define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg)) -#define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg)) - /* Intel GPIO access functions */ #define I2C_RISEFALL_TIME 20 @@ -74,8 +71,7 @@ struct intel_gpio { void gma_intel_i2c_reset(struct drm_device *dev) { - struct drm_psb_private *dev_priv = dev->dev_private; - GMBUS_REG_WRITE(GMBUS0, 0); + REG_WRITE(GMBUS0, 0); } static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable) @@ -102,10 +98,11 @@ static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable) static u32 get_reserved(struct intel_gpio *gpio) { struct drm_psb_private *dev_priv = gpio->dev_priv; + struct drm_device *dev = dev_priv->dev; u32 reserved = 0; /* On most chips, these bits must be preserved in software. */ - reserved = GMBUS_REG_READ(gpio->reg) & + reserved = REG_READ(gpio->reg) & (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); @@ -116,26 +113,29 @@ static int get_clock(void *data) { struct intel_gpio *gpio = data; struct drm_psb_private *dev_priv = gpio->dev_priv; + struct drm_device *dev = dev_priv->dev; u32 reserved = get_reserved(gpio); - GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK); - GMBUS_REG_WRITE(gpio->reg, reserved); - return (GMBUS_REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0; + REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK); + REG_WRITE(gpio->reg, reserved); + return (REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0; } static int get_data(void *data) { struct intel_gpio *gpio = data; struct drm_psb_private *dev_priv = gpio->dev_priv; + struct drm_device *dev = dev_priv->dev; u32 reserved = get_reserved(gpio); - GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK); - GMBUS_REG_WRITE(gpio->reg, reserved); - return (GMBUS_REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0; + REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK); + REG_WRITE(gpio->reg, reserved); + return (REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0; } static void set_clock(void *data, int state_high) { struct intel_gpio *gpio = data; struct drm_psb_private *dev_priv = gpio->dev_priv; + struct drm_device *dev = dev_priv->dev; u32 reserved = get_reserved(gpio); u32 clock_bits; @@ -145,14 +145,15 @@ static void set_clock(void *data, int state_high) clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK; - GMBUS_REG_WRITE(gpio->reg, reserved | clock_bits); - GMBUS_REG_READ(gpio->reg); /* Posting */ + REG_WRITE(gpio->reg, reserved | clock_bits); + REG_READ(gpio->reg); /* Posting */ } static void set_data(void *data, int state_high) { struct intel_gpio *gpio = data; struct drm_psb_private *dev_priv = gpio->dev_priv; + struct drm_device *dev = dev_priv->dev; u32 reserved = get_reserved(gpio); u32 data_bits; @@ -162,8 +163,8 @@ static void set_data(void *data, int state_high) data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK; - GMBUS_REG_WRITE(gpio->reg, reserved | data_bits); - GMBUS_REG_READ(gpio->reg); + REG_WRITE(gpio->reg, reserved | data_bits); + REG_READ(gpio->reg); } static struct i2c_adapter * @@ -250,6 +251,7 @@ gmbus_xfer(struct i2c_adapter *adapter, struct intel_gmbus, adapter); struct drm_psb_private *dev_priv = adapter->algo_data; + struct drm_device *dev = dev_priv->dev; int i, reg_offset; if (bus->force_bit) @@ -258,30 +260,28 @@ gmbus_xfer(struct i2c_adapter *adapter, reg_offset = 0; - GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0); + REG_WRITE(GMBUS0 + reg_offset, bus->reg0); for (i = 0; i < num; i++) { u16 len = msgs[i].len; u8 *buf = msgs[i].buf; if (msgs[i].flags & I2C_M_RD) { - GMBUS_REG_WRITE(GMBUS1 + reg_offset, - GMBUS_CYCLE_WAIT | - (i + 1 == num ? GMBUS_CYCLE_STOP : 0) | - (len << GMBUS_BYTE_COUNT_SHIFT) | - (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) | - GMBUS_SLAVE_READ | GMBUS_SW_RDY); - GMBUS_REG_READ(GMBUS2+reg_offset); + REG_WRITE(GMBUS1 + reg_offset, + GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) | + (len << GMBUS_BYTE_COUNT_SHIFT) | + (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) | + GMBUS_SLAVE_READ | GMBUS_SW_RDY); + REG_READ(GMBUS2+reg_offset); do { u32 val, loop = 0; - if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & - (GMBUS_SATOER | GMBUS_HW_RDY), 50)) + if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) goto timeout; - if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) + if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) goto clear_err; - val = GMBUS_REG_READ(GMBUS3 + reg_offset); + val = REG_READ(GMBUS3 + reg_offset); do { *buf++ = val & 0xff; val >>= 8; @@ -295,20 +295,18 @@ gmbus_xfer(struct i2c_adapter *adapter, val |= *buf++ << (8 * loop); } while (--len && ++loop < 4); - GMBUS_REG_WRITE(GMBUS3 + reg_offset, val); - GMBUS_REG_WRITE(GMBUS1 + reg_offset, + REG_WRITE(GMBUS3 + reg_offset, val); + REG_WRITE(GMBUS1 + reg_offset, (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) | (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) | (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); - GMBUS_REG_READ(GMBUS2+reg_offset); + REG_READ(GMBUS2+reg_offset); while (len) { - if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & - (GMBUS_SATOER | GMBUS_HW_RDY), 50)) + if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) goto timeout; - if (GMBUS_REG_READ(GMBUS2 + reg_offset) & - GMBUS_SATOER) + if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) goto clear_err; val = loop = 0; @@ -316,14 +314,14 @@ gmbus_xfer(struct i2c_adapter *adapter, val |= *buf++ << (8 * loop); } while (--len && ++loop < 4); - GMBUS_REG_WRITE(GMBUS3 + reg_offset, val); - GMBUS_REG_READ(GMBUS2+reg_offset); + REG_WRITE(GMBUS3 + reg_offset, val); + REG_READ(GMBUS2+reg_offset); } } - if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50)) + if (i + 1 < num && wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50)) goto timeout; - if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) + if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) goto clear_err; } @@ -334,20 +332,20 @@ clear_err: * of resetting the GMBUS controller and so clearing the * BUS_ERROR raised by the slave's NAK. */ - GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); - GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0); + REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); + REG_WRITE(GMBUS1 + reg_offset, 0); done: /* Mark the GMBUS interface as disabled. We will re-enable it at the * start of the next xfer, till then let it sleep. */ - GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0); + REG_WRITE(GMBUS0 + reg_offset, 0); return i; timeout: DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n", bus->reg0 & 0xff, bus->adapter.name); - GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0); + REG_WRITE(GMBUS0 + reg_offset, 0); /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff); @@ -401,11 +399,6 @@ int gma_intel_setup_gmbus(struct drm_device *dev) if (dev_priv->gmbus == NULL) return -ENOMEM; - if (IS_MRST(dev)) - dev_priv->gmbus_reg = dev_priv->aux_reg; - else - dev_priv->gmbus_reg = dev_priv->vdc_reg; - for (i = 0; i < GMBUS_NUM_PORTS; i++) { struct intel_gmbus *bus = &dev_priv->gmbus[i]; @@ -494,7 +487,6 @@ void gma_intel_teardown_gmbus(struct drm_device *dev) i2c_del_adapter(&bus->adapter); } - dev_priv->gmbus_reg = NULL; /* iounmap is done in driver_unload */ kfree(dev_priv->gmbus); dev_priv->gmbus = NULL; } |