diff options
Diffstat (limited to 'drivers/gpu/drm/gma500/oaktrail_crtc.c')
-rw-r--r-- | drivers/gpu/drm/gma500/oaktrail_crtc.c | 433 |
1 files changed, 164 insertions, 269 deletions
diff --git a/drivers/gpu/drm/gma500/oaktrail_crtc.c b/drivers/gpu/drm/gma500/oaktrail_crtc.c index 8195e85..54c9896 100644 --- a/drivers/gpu/drm/gma500/oaktrail_crtc.c +++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c @@ -26,10 +26,24 @@ #include "gma_display.h" #include "power.h" -#define MRST_LIMIT_LVDS_100L 0 -#define MRST_LIMIT_LVDS_83 1 -#define MRST_LIMIT_LVDS_100 2 -#define MRST_LIMIT_SDVO 3 +struct psb_intel_range_t { + int min, max; +}; + +struct oaktrail_limit_t { + struct psb_intel_range_t dot, m, p1; +}; + +struct oaktrail_clock_t { + /* derived values */ + int dot; + int m; + int p1; +}; + +#define MRST_LIMIT_LVDS_100L 0 +#define MRST_LIMIT_LVDS_83 1 +#define MRST_LIMIT_LVDS_100 2 #define MRST_DOT_MIN 19750 #define MRST_DOT_MAX 120000 @@ -43,40 +57,21 @@ #define MRST_P1_MAX_0 7 #define MRST_P1_MAX_1 8 -static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit, - struct drm_crtc *crtc, int target, - int refclk, struct gma_clock_t *best_clock); - -static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit, - struct drm_crtc *crtc, int target, - int refclk, struct gma_clock_t *best_clock); - -static const struct gma_limit_t mrst_limits[] = { +static const struct oaktrail_limit_t oaktrail_limits[] = { { /* MRST_LIMIT_LVDS_100L */ .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX}, .m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L}, .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1}, - .find_pll = mrst_lvds_find_best_pll, }, { /* MRST_LIMIT_LVDS_83L */ .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX}, .m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83}, .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0}, - .find_pll = mrst_lvds_find_best_pll, }, { /* MRST_LIMIT_LVDS_100 */ .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX}, .m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100}, .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1}, - .find_pll = mrst_lvds_find_best_pll, - }, - { /* MRST_LIMIT_SDVO */ - .vco = {.min = 1400000, .max = 2800000}, - .n = {.min = 3, .max = 7}, - .m = {.min = 80, .max = 137}, - .p1 = {.min = 1, .max = 2}, - .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 10}, - .find_pll = mrst_sdvo_find_best_pll, }, }; @@ -87,10 +82,9 @@ static const u32 oaktrail_m_converts[] = { 0x12, 0x09, 0x24, 0x32, 0x39, 0x1c, }; -static const struct gma_limit_t *mrst_limit(struct drm_crtc *crtc, - int refclk) +static const struct oaktrail_limit_t *oaktrail_limit(struct drm_crtc *crtc) { - const struct gma_limit_t *limit = NULL; + const struct oaktrail_limit_t *limit = NULL; struct drm_device *dev = crtc->dev; struct drm_psb_private *dev_priv = dev->dev_private; @@ -98,100 +92,45 @@ static const struct gma_limit_t *mrst_limit(struct drm_crtc *crtc, || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) { switch (dev_priv->core_freq) { case 100: - limit = &mrst_limits[MRST_LIMIT_LVDS_100L]; + limit = &oaktrail_limits[MRST_LIMIT_LVDS_100L]; break; case 166: - limit = &mrst_limits[MRST_LIMIT_LVDS_83]; + limit = &oaktrail_limits[MRST_LIMIT_LVDS_83]; break; case 200: - limit = &mrst_limits[MRST_LIMIT_LVDS_100]; + limit = &oaktrail_limits[MRST_LIMIT_LVDS_100]; break; } - } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { - limit = &mrst_limits[MRST_LIMIT_SDVO]; } else { limit = NULL; - dev_err(dev->dev, "mrst_limit Wrong display type.\n"); + dev_err(dev->dev, "oaktrail_limit Wrong display type.\n"); } return limit; } /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ -static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) +static void oaktrail_clock(int refclk, struct oaktrail_clock_t *clock) { clock->dot = (refclk * clock->m) / (14 * clock->p1); } -static void mrst_print_pll(struct gma_clock_t *clock) +static void mrstPrintPll(char *prefix, struct oaktrail_clock_t *clock) { - DRM_DEBUG_DRIVER("dotclock=%d, m=%d, m1=%d, m2=%d, n=%d, p1=%d, p2=%d\n", - clock->dot, clock->m, clock->m1, clock->m2, clock->n, - clock->p1, clock->p2); -} - -static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit, - struct drm_crtc *crtc, int target, - int refclk, struct gma_clock_t *best_clock) -{ - struct gma_clock_t clock; - u32 target_vco, actual_freq; - s32 freq_error, min_error = 100000; - - memset(best_clock, 0, sizeof(*best_clock)); - - for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { - for (clock.n = limit->n.min; clock.n <= limit->n.max; - clock.n++) { - for (clock.p1 = limit->p1.min; - clock.p1 <= limit->p1.max; clock.p1++) { - /* p2 value always stored in p2_slow on SDVO */ - clock.p = clock.p1 * limit->p2.p2_slow; - target_vco = target * clock.p; - - /* VCO will increase at this point so break */ - if (target_vco > limit->vco.max) - break; - - if (target_vco < limit->vco.min) - continue; - - actual_freq = (refclk * clock.m) / - (clock.n * clock.p); - freq_error = 10000 - - ((target * 10000) / actual_freq); - - if (freq_error < -min_error) { - /* freq_error will start to decrease at - this point so break */ - break; - } - - if (freq_error < 0) - freq_error = -freq_error; - - if (freq_error < min_error) { - min_error = freq_error; - *best_clock = clock; - } - } - } - if (min_error == 0) - break; - } - - return min_error == 0; + pr_debug("%s: dotclock = %d, m = %d, p1 = %d.\n", + prefix, clock->dot, clock->m, clock->p1); } /** * Returns a set of divisors for the desired target clock with the given refclk, * or FALSE. Divisor values are the actual divisors for */ -static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit, - struct drm_crtc *crtc, int target, - int refclk, struct gma_clock_t *best_clock) +static bool +mrstFindBestPLL(struct drm_crtc *crtc, int target, int refclk, + struct oaktrail_clock_t *best_clock) { - struct gma_clock_t clock; + struct oaktrail_clock_t clock; + const struct oaktrail_limit_t *limit = oaktrail_limit(crtc); int err = target; memset(best_clock, 0, sizeof(*best_clock)); @@ -201,7 +140,7 @@ static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit, clock.p1++) { int this_err; - mrst_lvds_clock(refclk, &clock); + oaktrail_clock(refclk, &clock); this_err = abs(clock.dot - target); if (this_err < err) { @@ -210,6 +149,7 @@ static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit, } } } + dev_dbg(crtc->dev->dev, "mrstFindBestPLL err = %d.\n", err); return err != target; } @@ -227,10 +167,8 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) int pipe = gma_crtc->pipe; const struct psb_offset *map = &dev_priv->regmap[pipe]; u32 temp; - int i; - int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0; - if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { + if (pipe == 1) { oaktrail_crtc_hdmi_dpms(crtc, mode); return; } @@ -245,45 +183,35 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) case DRM_MODE_DPMS_ON: case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: - for (i = 0; i <= need_aux; i++) { - /* Enable the DPLL */ - temp = REG_READ_WITH_AUX(map->dpll, i); - if ((temp & DPLL_VCO_ENABLE) == 0) { - REG_WRITE_WITH_AUX(map->dpll, temp, i); - REG_READ_WITH_AUX(map->dpll, i); - /* Wait for the clocks to stabilize. */ - udelay(150); - REG_WRITE_WITH_AUX(map->dpll, - temp | DPLL_VCO_ENABLE, i); - REG_READ_WITH_AUX(map->dpll, i); - /* Wait for the clocks to stabilize. */ - udelay(150); - REG_WRITE_WITH_AUX(map->dpll, - temp | DPLL_VCO_ENABLE, i); - REG_READ_WITH_AUX(map->dpll, i); - /* Wait for the clocks to stabilize. */ - udelay(150); - } - - /* Enable the pipe */ - temp = REG_READ_WITH_AUX(map->conf, i); - if ((temp & PIPEACONF_ENABLE) == 0) { - REG_WRITE_WITH_AUX(map->conf, - temp | PIPEACONF_ENABLE, i); - } - - /* Enable the plane */ - temp = REG_READ_WITH_AUX(map->cntr, i); - if ((temp & DISPLAY_PLANE_ENABLE) == 0) { - REG_WRITE_WITH_AUX(map->cntr, - temp | DISPLAY_PLANE_ENABLE, - i); - /* Flush the plane changes */ - REG_WRITE_WITH_AUX(map->base, - REG_READ_WITH_AUX(map->base, i), i); - } - + /* Enable the DPLL */ + temp = REG_READ(map->dpll); + if ((temp & DPLL_VCO_ENABLE) == 0) { + REG_WRITE(map->dpll, temp); + REG_READ(map->dpll); + /* Wait for the clocks to stabilize. */ + udelay(150); + REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); + REG_READ(map->dpll); + /* Wait for the clocks to stabilize. */ + udelay(150); + REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); + REG_READ(map->dpll); + /* Wait for the clocks to stabilize. */ + udelay(150); + } + /* Enable the pipe */ + temp = REG_READ(map->conf); + if ((temp & PIPEACONF_ENABLE) == 0) + REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); + /* Enable the plane */ + temp = REG_READ(map->cntr); + if ((temp & DISPLAY_PLANE_ENABLE) == 0) { + REG_WRITE(map->cntr, + temp | DISPLAY_PLANE_ENABLE); + /* Flush the plane changes */ + REG_WRITE(map->base, REG_READ(map->base)); } + gma_crtc_load_lut(crtc); /* Give the overlay scaler a chance to enable @@ -295,52 +223,48 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) * if it's on this pipe */ /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ - for (i = 0; i <= need_aux; i++) { - /* Disable the VGA plane that we never use */ - REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i); - /* Disable display plane */ - temp = REG_READ_WITH_AUX(map->cntr, i); - if ((temp & DISPLAY_PLANE_ENABLE) != 0) { - REG_WRITE_WITH_AUX(map->cntr, - temp & ~DISPLAY_PLANE_ENABLE, i); - /* Flush the plane changes */ - REG_WRITE_WITH_AUX(map->base, - REG_READ(map->base), i); - REG_READ_WITH_AUX(map->base, i); - } + /* Disable the VGA plane that we never use */ + REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); + /* Disable display plane */ + temp = REG_READ(map->cntr); + if ((temp & DISPLAY_PLANE_ENABLE) != 0) { + REG_WRITE(map->cntr, + temp & ~DISPLAY_PLANE_ENABLE); + /* Flush the plane changes */ + REG_WRITE(map->base, REG_READ(map->base)); + REG_READ(map->base); + } - /* Next, disable display pipes */ - temp = REG_READ_WITH_AUX(map->conf, i); - if ((temp & PIPEACONF_ENABLE) != 0) { - REG_WRITE_WITH_AUX(map->conf, - temp & ~PIPEACONF_ENABLE, i); - REG_READ_WITH_AUX(map->conf, i); - } - /* Wait for for the pipe disable to take effect. */ - gma_wait_for_vblank(dev); - - temp = REG_READ_WITH_AUX(map->dpll, i); - if ((temp & DPLL_VCO_ENABLE) != 0) { - REG_WRITE_WITH_AUX(map->dpll, - temp & ~DPLL_VCO_ENABLE, i); - REG_READ_WITH_AUX(map->dpll, i); - } + /* Next, disable display pipes */ + temp = REG_READ(map->conf); + if ((temp & PIPEACONF_ENABLE) != 0) { + REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); + REG_READ(map->conf); + } + /* Wait for for the pipe disable to take effect. */ + gma_wait_for_vblank(dev); - /* Wait for the clocks to turn off. */ - udelay(150); + temp = REG_READ(map->dpll); + if ((temp & DPLL_VCO_ENABLE) != 0) { + REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); + REG_READ(map->dpll); } + + /* Wait for the clocks to turn off. */ + udelay(150); break; } - /* Set FIFO Watermarks (values taken from EMGD) */ - REG_WRITE(DSPARB, 0x3f80); - REG_WRITE(DSPFW1, 0x3f8f0404); - REG_WRITE(DSPFW2, 0x04040f04); + /*Set FIFO Watermarks*/ + REG_WRITE(DSPARB, 0x3FFF); + REG_WRITE(DSPFW1, 0x3F88080A); + REG_WRITE(DSPFW2, 0x0b060808); REG_WRITE(DSPFW3, 0x0); - REG_WRITE(DSPFW4, 0x04040404); + REG_WRITE(DSPFW4, 0x08030404); REG_WRITE(DSPFW5, 0x04040404); REG_WRITE(DSPFW6, 0x78); - REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040); + REG_WRITE(0x70400, REG_READ(0x70400) | 0x4000); + /* Must write Bit 14 of the Chicken Bit Register */ gma_power_end(dev); } @@ -373,8 +297,7 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, int pipe = gma_crtc->pipe; const struct psb_offset *map = &dev_priv->regmap[pipe]; int refclk = 0; - struct gma_clock_t clock; - const struct gma_limit_t *limit; + struct oaktrail_clock_t clock; u32 dpll = 0, fp = 0, dspcntr, pipeconf; bool ok, is_sdvo = false; bool is_lvds = false; @@ -383,10 +306,8 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, struct gma_encoder *gma_encoder = NULL; uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN; struct drm_connector *connector; - int i; - int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0; - if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) + if (pipe == 1) return oaktrail_crtc_hdmi_mode_set(crtc, mode, adjusted_mode, x, y, old_fb); if (!gma_power_begin(dev, true)) @@ -419,17 +340,15 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, } /* Disable the VGA plane that we never use */ - for (i = 0; i <= need_aux; i++) - REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i); + REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); /* Disable the panel fitter if it was on our pipe */ if (oaktrail_panel_fitter_pipe(dev) == pipe) REG_WRITE(PFIT_CONTROL, 0); - for (i = 0; i <= need_aux; i++) { - REG_WRITE_WITH_AUX(map->src, ((mode->crtc_hdisplay - 1) << 16) | - (mode->crtc_vdisplay - 1), i); - } + REG_WRITE(map->src, + ((mode->crtc_hdisplay - 1) << 16) | + (mode->crtc_vdisplay - 1)); if (gma_encoder) drm_object_property_get_value(&connector->base, @@ -446,39 +365,35 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, offsetY = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; - for (i = 0; i <= need_aux; i++) { - REG_WRITE_WITH_AUX(map->htotal, (mode->crtc_hdisplay - 1) | - ((adjusted_mode->crtc_htotal - 1) << 16), i); - REG_WRITE_WITH_AUX(map->vtotal, (mode->crtc_vdisplay - 1) | - ((adjusted_mode->crtc_vtotal - 1) << 16), i); - REG_WRITE_WITH_AUX(map->hblank, - (adjusted_mode->crtc_hblank_start - offsetX - 1) | - ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16), i); - REG_WRITE_WITH_AUX(map->hsync, - (adjusted_mode->crtc_hsync_start - offsetX - 1) | - ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16), i); - REG_WRITE_WITH_AUX(map->vblank, - (adjusted_mode->crtc_vblank_start - offsetY - 1) | - ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16), i); - REG_WRITE_WITH_AUX(map->vsync, - (adjusted_mode->crtc_vsync_start - offsetY - 1) | - ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16), i); - } + REG_WRITE(map->htotal, (mode->crtc_hdisplay - 1) | + ((adjusted_mode->crtc_htotal - 1) << 16)); + REG_WRITE(map->vtotal, (mode->crtc_vdisplay - 1) | + ((adjusted_mode->crtc_vtotal - 1) << 16)); + REG_WRITE(map->hblank, + (adjusted_mode->crtc_hblank_start - offsetX - 1) | + ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16)); + REG_WRITE(map->hsync, + (adjusted_mode->crtc_hsync_start - offsetX - 1) | + ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16)); + REG_WRITE(map->vblank, + (adjusted_mode->crtc_vblank_start - offsetY - 1) | + ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16)); + REG_WRITE(map->vsync, + (adjusted_mode->crtc_vsync_start - offsetY - 1) | + ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16)); } else { - for (i = 0; i <= need_aux; i++) { - REG_WRITE_WITH_AUX(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | - ((adjusted_mode->crtc_htotal - 1) << 16), i); - REG_WRITE_WITH_AUX(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | - ((adjusted_mode->crtc_vtotal - 1) << 16), i); - REG_WRITE_WITH_AUX(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | - ((adjusted_mode->crtc_hblank_end - 1) << 16), i); - REG_WRITE_WITH_AUX(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | - ((adjusted_mode->crtc_hsync_end - 1) << 16), i); - REG_WRITE_WITH_AUX(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | - ((adjusted_mode->crtc_vblank_end - 1) << 16), i); - REG_WRITE_WITH_AUX(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | - ((adjusted_mode->crtc_vsync_end - 1) << 16), i); - } + REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | + ((adjusted_mode->crtc_htotal - 1) << 16)); + REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | + ((adjusted_mode->crtc_vtotal - 1) << 16)); + REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | + ((adjusted_mode->crtc_hblank_end - 1) << 16)); + REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | + ((adjusted_mode->crtc_hsync_end - 1) << 16)); + REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | + ((adjusted_mode->crtc_vblank_end - 1) << 16)); + REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | + ((adjusted_mode->crtc_vsync_end - 1) << 16)); } /* Flush the plane changes */ @@ -503,30 +418,21 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, if (is_mipi) goto oaktrail_crtc_mode_set_exit; + refclk = dev_priv->core_freq * 1000; dpll = 0; /*BIT16 = 0 for 100MHz reference */ - refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000; - limit = mrst_limit(crtc, refclk); - ok = limit->find_pll(limit, crtc, adjusted_mode->clock, - refclk, &clock); + ok = mrstFindBestPLL(crtc, adjusted_mode->clock, refclk, &clock); - if (is_sdvo) { - /* Convert calculated values to register values */ - clock.p1 = (1L << (clock.p1 - 1)); - clock.m -= 2; - clock.n = (1L << (clock.n - 1)); + if (!ok) { + dev_dbg(dev->dev, "mrstFindBestPLL fail in oaktrail_crtc_mode_set.\n"); + } else { + dev_dbg(dev->dev, "oaktrail_crtc_mode_set pixel clock = %d," + "m = %x, p1 = %x.\n", clock.dot, clock.m, + clock.p1); } - if (!ok) - DRM_ERROR("Failed to find proper PLL settings"); - - mrst_print_pll(&clock); - - if (is_sdvo) - fp = clock.n << 16 | clock.m; - else - fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8; + fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8; dpll |= DPLL_VGA_MODE_DIS; @@ -550,43 +456,38 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, /* compute bitmask from p1 value */ - if (is_sdvo) - dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16; - else - dpll |= (1 << (clock.p1 - 2)) << 17; + dpll |= (1 << (clock.p1 - 2)) << 17; dpll |= DPLL_VCO_ENABLE; + mrstPrintPll("chosen", &clock); + if (dpll & DPLL_VCO_ENABLE) { - for (i = 0; i <= need_aux; i++) { - REG_WRITE_WITH_AUX(map->fp0, fp, i); - REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); - REG_READ_WITH_AUX(map->dpll, i); - /* Check the DPLLA lock bit PIPEACONF[29] */ - udelay(150); - } + REG_WRITE(map->fp0, fp); + REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); + REG_READ(map->dpll); + /* Check the DPLLA lock bit PIPEACONF[29] */ + udelay(150); } - for (i = 0; i <= need_aux; i++) { - REG_WRITE_WITH_AUX(map->fp0, fp, i); - REG_WRITE_WITH_AUX(map->dpll, dpll, i); - REG_READ_WITH_AUX(map->dpll, i); - /* Wait for the clocks to stabilize. */ - udelay(150); + REG_WRITE(map->fp0, fp); + REG_WRITE(map->dpll, dpll); + REG_READ(map->dpll); + /* Wait for the clocks to stabilize. */ + udelay(150); - /* write it again -- the BIOS does, after all */ - REG_WRITE_WITH_AUX(map->dpll, dpll, i); - REG_READ_WITH_AUX(map->dpll, i); - /* Wait for the clocks to stabilize. */ - udelay(150); + /* write it again -- the BIOS does, after all */ + REG_WRITE(map->dpll, dpll); + REG_READ(map->dpll); + /* Wait for the clocks to stabilize. */ + udelay(150); - REG_WRITE_WITH_AUX(map->conf, pipeconf, i); - REG_READ_WITH_AUX(map->conf, i); - gma_wait_for_vblank(dev); + REG_WRITE(map->conf, pipeconf); + REG_READ(map->conf); + gma_wait_for_vblank(dev); - REG_WRITE_WITH_AUX(map->cntr, dspcntr, i); - gma_wait_for_vblank(dev); - } + REG_WRITE(map->cntr, dspcntr); + gma_wait_for_vblank(dev); oaktrail_crtc_mode_set_exit: gma_power_end(dev); @@ -664,9 +565,3 @@ const struct drm_crtc_helper_funcs oaktrail_helper_funcs = { .commit = gma_crtc_commit, }; -/* Not used yet */ -const struct gma_clock_funcs mrst_clock_funcs = { - .clock = mrst_lvds_clock, - .limit = mrst_limit, - .pll_is_valid = gma_pll_is_valid, -}; |