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path: root/drivers/gpu/drm/i915/intel_ddi.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4b5366b..c3d0653 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -888,32 +888,32 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
int type = intel_encoder->type;
uint32_t temp;
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
- temp = PIPE_MSA_SYNC_CLK;
+ temp = TRANS_MSA_SYNC_CLK;
switch (intel_crtc->bpp) {
case 18:
- temp |= PIPE_MSA_6_BPC;
+ temp |= TRANS_MSA_6_BPC;
break;
case 24:
- temp |= PIPE_MSA_8_BPC;
+ temp |= TRANS_MSA_8_BPC;
break;
case 30:
- temp |= PIPE_MSA_10_BPC;
+ temp |= TRANS_MSA_10_BPC;
break;
case 36:
- temp |= PIPE_MSA_12_BPC;
+ temp |= TRANS_MSA_12_BPC;
break;
default:
- temp |= PIPE_MSA_8_BPC;
- WARN(1, "%d bpp unsupported by pipe DDI function\n",
+ temp |= TRANS_MSA_8_BPC;
+ WARN(1, "%d bpp unsupported by DDI function\n",
intel_crtc->bpp);
}
- I915_WRITE(PIPE_MSA_MISC(pipe), temp);
+ I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
}
}