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path: root/drivers/mtd/spi-nor/spi-nor.c
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Diffstat (limited to 'drivers/mtd/spi-nor/spi-nor.c')
-rw-r--r--drivers/mtd/spi-nor/spi-nor.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 792354a..67b6fce 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -856,6 +856,9 @@ static int set_ddr_quad_mode(struct spi_nor *nor, u32 jedec_id)
return status;
}
return status;
+ case CFI_MFR_ST: /* Micron, actually */
+ /* DTR quad read works with the Extended SPI protocol. */
+ return 0;
default:
return -EINVAL;
}
@@ -1055,6 +1058,8 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
case SPI_NOR_DDR_QUAD:
if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) { /* Spansion */
nor->read_opcode = SPINOR_OP_READ_1_4_4_D;
+ } else if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
+ nor->read_opcode = SPINOR_OP_READ_1_1_4_D;
} else {
dev_err(dev, "DDR Quad Read is not supported.\n");
return -EINVAL;