diff options
Diffstat (limited to 'drivers/net/ethernet/freescale/fman/inc')
15 files changed, 1818 insertions, 65 deletions
diff --git a/drivers/net/ethernet/freescale/fman/inc/Peripherals/dpaa_ext.h b/drivers/net/ethernet/freescale/fman/inc/Peripherals/dpaa_ext.h index c20a6eb..66fa760 100644 --- a/drivers/net/ethernet/freescale/fman/inc/Peripherals/dpaa_ext.h +++ b/drivers/net/ethernet/freescale/fman/inc/Peripherals/dpaa_ext.h @@ -199,6 +199,8 @@ do { \ #pragma pack(pop) #endif /* defined(__MWERKS__) && ... */ +#define DPAA_LIODN_DONT_OVERRIDE (-1) + /** @} */ /* end of DPAA_grp group */ diff --git a/drivers/net/ethernet/freescale/fman/inc/Peripherals/fm_mac_ext.h b/drivers/net/ethernet/freescale/fman/inc/Peripherals/fm_mac_ext.h index 94b305c..b7128b5 100644 --- a/drivers/net/ethernet/freescale/fman/inc/Peripherals/fm_mac_ext.h +++ b/drivers/net/ethernet/freescale/fman/inc/Peripherals/fm_mac_ext.h @@ -210,7 +210,11 @@ typedef struct t_FmMacStatistics { typedef struct t_FmMacParams { uintptr_t baseAddr; /**< Base of memory mapped FM MAC registers */ t_EnetAddr addr; /**< MAC address of device; First octet is sent first */ - uint8_t macId; /**< MAC ID <dTSEC 0-3> <10G-MAC 0> */ + uint8_t macId; /**< MAC ID; + numbering of dTSEC and 1G-mEMAC: + 0 - FM_MAX_NUM_OF_1G_MACS; + numbering of 10G-MAC (TGEC) and 10G-mEMAC: + 0 - FM_MAX_NUM_OF_10G_MACS */ e_EnetMode enetMode; /**< Ethernet operation mode (MAC-PHY interface and speed); Note that the speed should indicate the maximum rate that this MAC should support rather than the actual speed; diff --git a/drivers/net/ethernet/freescale/fman/inc/Peripherals/fm_pcd_ext.h b/drivers/net/ethernet/freescale/fman/inc/Peripherals/fm_pcd_ext.h index 00750ba..83cf237 100644 --- a/drivers/net/ethernet/freescale/fman/inc/Peripherals/fm_pcd_ext.h +++ b/drivers/net/ethernet/freescale/fman/inc/Peripherals/fm_pcd_ext.h @@ -47,7 +47,6 @@ /**************************************************************************//** - @Group FM_grp Frame Manager API @Description Frame Manager Application Programming Interface @@ -2538,6 +2537,7 @@ typedef struct t_FmPcdManipReassemParams { } u; } t_FmPcdManipReassemParams; + /**************************************************************************//** @Description Parameters for defining a manipulation node *//***************************************************************************/ @@ -2935,6 +2935,10 @@ t_Error FM_PCD_MatchTableDelete(t_Handle h_CcNode); @Cautions Allowed only following FM_PCD_MatchTableSet(); Not relevant in the case the node is of type 'INDEXED_LOOKUP'. + When configuring nextEngine = e_FM_PCD_CC, note that + p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different + from the currently changed table. + *//***************************************************************************/ t_Error FM_PCD_MatchTableModifyMissNextEngine(t_Handle h_CcNode, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams); @@ -2992,6 +2996,10 @@ t_Error FM_PCD_MatchTableAddKey(t_Handle h_CcNode, @Return E_OK on success; Error code otherwise. @Cautions Allowed only following FM_PCD_MatchTableSet(). + When configuring nextEngine = e_FM_PCD_CC, note that + p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different + from the currently changed table. + *//***************************************************************************/ t_Error FM_PCD_MatchTableModifyNextEngine(t_Handle h_CcNode, uint16_t keyIndex, @@ -3013,6 +3021,9 @@ t_Error FM_PCD_MatchTableModifyNextEngine(t_Handle h_CcNode, @Cautions Allowed only following FM_PCD_MatchTableSet() was called for this node and the nodes that lead to it. + When configuring nextEngine = e_FM_PCD_CC, note that + p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different + from the currently changed table. *//***************************************************************************/ t_Error FM_PCD_MatchTableModifyKeyAndNextEngine(t_Handle h_CcNode, uint16_t keyIndex, @@ -3082,6 +3093,9 @@ t_Error FM_PCD_MatchTableFindNRemoveKey(t_Handle h_CcNode, @Return E_OK on success; Error code otherwise. @Cautions Allowed only following FM_PCD_MatchTableSet(). + When configuring nextEngine = e_FM_PCD_CC, note that + p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different + from the currently changed table. *//***************************************************************************/ t_Error FM_PCD_MatchTableFindNModifyNextEngine(t_Handle h_CcNode, uint8_t keySize, @@ -3108,6 +3122,9 @@ t_Error FM_PCD_MatchTableFindNModifyNextEngine(t_Handle h_CcNod @Cautions Allowed only following FM_PCD_MatchTableSet() was called for this node and the nodes that lead to it. + When configuring nextEngine = e_FM_PCD_CC, note that + p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different + from the currently changed table. *//***************************************************************************/ t_Error FM_PCD_MatchTableFindNModifyKeyAndNextEngine(t_Handle h_CcNode, uint8_t keySize, @@ -3390,6 +3407,9 @@ t_Error FM_PCD_HashTableRemoveKey(t_Handle h_HashTbl, @Return E_OK on success; Error code otherwise. @Cautions Allowed only following FM_PCD_HashTableSet(). + When configuring nextEngine = e_FM_PCD_CC, note that + p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different + from the currently changed table. *//***************************************************************************/ t_Error FM_PCD_HashTableModifyNextEngine(t_Handle h_HashTbl, uint8_t keySize, @@ -3408,6 +3428,9 @@ t_Error FM_PCD_HashTableModifyNextEngine(t_Handle h_HashTbl, @Return E_OK on success; Error code otherwise. @Cautions Allowed only following FM_PCD_HashTableSet(). + When configuring nextEngine = e_FM_PCD_CC, note that + p_FmPcdCcNextEngineParams->ccParams.h_CcNode must be different + from the currently changed table. *//***************************************************************************/ t_Error FM_PCD_HashTableModifyMissNextEngine(t_Handle h_HashTbl, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams); diff --git a/drivers/net/ethernet/freescale/fman/inc/Peripherals/fm_port_ext.h b/drivers/net/ethernet/freescale/fman/inc/Peripherals/fm_port_ext.h index 89fabbc..6f344b8 100644 --- a/drivers/net/ethernet/freescale/fman/inc/Peripherals/fm_port_ext.h +++ b/drivers/net/ethernet/freescale/fman/inc/Peripherals/fm_port_ext.h @@ -136,7 +136,7 @@ typedef uint32_t fmPortFrameErrSelect_t; /**< typedef #define FM_PORT_FRM_ERR_IPRE (FM_FD_ERR_IPR & ~FM_FD_IPR) /**< IPR error */ #define FM_PORT_FRM_ERR_IPR_NCSP (FM_FD_ERR_IPR_NCSP & ~FM_FD_IPR) /**< IPR non-consistent-sp */ -#define FM_PORT_FRM_ERR_IPFE 0 /**< Obsolete; will be removed in the future */ +#define FM_PORT_FRM_ERR_IPFE 0 /**< Obsolete; will be removed in the future */ #ifdef FM_CAPWAP_SUPPORT #define FM_PORT_FRM_ERR_CRE FM_FD_ERR_CRE @@ -147,7 +147,7 @@ typedef uint32_t fmPortFrameErrSelect_t; /**< typedef error (SGMII and TBI modes), FIFO parity error. PHY Sequence error, PHY error control character detected. */ #define FM_PORT_FRM_ERR_SIZE FM_FD_ERR_SIZE /**< Frame too long OR Frame size exceeds max_length_frame */ -#define FM_PORT_FRM_ERR_CLS_DISCARD FM_FD_ERR_CLS_DISCARD /**< classification discard */ +#define FM_PORT_FRM_ERR_CLS_DISCARD FM_FD_ERR_CLS_DISCARD /**< indicates a classifier "drop" operation */ #define FM_PORT_FRM_ERR_EXTRACTION FM_FD_ERR_EXTRACTION /**< Extract Out of Frame */ #define FM_PORT_FRM_ERR_NO_SCHEME FM_FD_ERR_NO_SCHEME /**< No Scheme Selected */ #define FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW FM_FD_ERR_KEYSIZE_OVERFLOW /**< Keysize Overflow */ @@ -159,7 +159,7 @@ typedef uint32_t fmPortFrameErrSelect_t; /**< typedef #define FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT FM_FD_ERR_PRS_ILL_INSTRUCT /**< Invalid Soft Parser instruction */ #define FM_PORT_FRM_ERR_PRS_HDR_ERR FM_FD_ERR_PRS_HDR_ERR /**< Header error was identified during parsing */ #define FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED FM_FD_ERR_BLOCK_LIMIT_EXCEEDED /**< Frame parsed beyind 256 first bytes */ -#define FM_PORT_FRM_ERR_PROCESS_TIMEOUT 0x00000001 /**< FPM Frame Processing Timeout Exceeded */ +#define FM_PORT_FRM_ERR_PROCESS_TIMEOUT 0x00000001 /**< FPM Frame Processing Timeout Exceeded */ /* @} */ @@ -1093,9 +1093,10 @@ t_Error FM_PORT_ConfigTxFifoMinFillLevel(t_Handle h_FmPort, uint32_t minFillLeve pipeline depth parameter in the internal driver data base from its default configuration: 1G ports: [DEFAULT_PORT_fifoDeqPipelineDepth_1G], - 10G port: [DEFAULT_PORT_fifoDeqPipelineDepth_10G] + 10G port: [DEFAULT_PORT_fifoDeqPipelineDepth_10G], + OP port: [DEFAULT_PORT_fifoDeqPipelineDepth_OH] - May be used for Tx ports only + May be used for Tx/OP ports only @Param[in] h_FmPort A handle to a FM Port module. @Param[in] deqPipelineDepth New value @@ -1907,13 +1908,7 @@ typedef struct t_FmPortPcdKgParams { @Description struct for defining policer parameters *//***************************************************************************/ typedef struct t_FmPortPcdPlcrParams { - t_Handle h_Profile; /**< Selected profile handle; Relevant for one of - following cases: - e_FM_PORT_PCD_SUPPORT_PLCR_ONLY or - e_FM_PORT_PCD_SUPPORT_PRS_AND_PLCR were selected, - or if any flow uses a KG scheme were policer - profile is not generated - (bypassPlcrProfileGeneration selected) */ + t_Handle h_Profile; /**< Selected profile handle */ } t_FmPortPcdPlcrParams; /**************************************************************************//** @@ -1926,7 +1921,13 @@ typedef struct t_FmPortPcdParams { t_FmPortPcdPrsParams *p_PrsParams; /**< Parser parameters for this port */ t_FmPortPcdCcParams *p_CcParams; /**< Coarse classification parameters for this port */ t_FmPortPcdKgParams *p_KgParams; /**< Keygen parameters for this port */ - t_FmPortPcdPlcrParams *p_PlcrParams; /**< Policer parameters for this port */ + t_FmPortPcdPlcrParams *p_PlcrParams; /**< Policer parameters for this port; Relevant for one of + following cases: + e_FM_PORT_PCD_SUPPORT_PLCR_ONLY or + e_FM_PORT_PCD_SUPPORT_PRS_AND_PLCR were selected, + or if any flow uses a KG scheme were policer + profile is not generated + ('bypassPlcrProfileGeneration selected'). */ t_Handle h_IpReassemblyManip;/**< IP Reassembly manipulation */ } t_FmPortPcdParams; @@ -2180,6 +2181,19 @@ t_Error FM_PORT_PcdKgUnbindSchemes (t_Handle h_FmPort, t_FmPcdPortSchemesParams *//***************************************************************************/ t_Error FM_PORT_PcdPrsModifyStartOffset (t_Handle h_FmPort, t_FmPcdPrsStart *p_FmPcdPrsStart); +/**************************************************************************//** + @Function FM_PORT_GetIPv4OptionsCount + + @Description TODO + + @Param[in] h_FmPort A handle to a FM Port module. + @Param[out] p_Ipv4OptionsCount will hold the counter value + + @Return E_OK on success; Error code otherwise. + + @Cautions Allowed only following FM_PORT_Init() +*//***************************************************************************/ +t_Error FM_PORT_GetIPv4OptionsCount(t_Handle h_FmPort, uint32_t *p_Ipv4OptionsCount); /** @} */ /* end of FM_PORT_pcd_runtime_control_grp group */ /** @} */ /* end of FM_PORT_runtime_control_grp group */ diff --git a/drivers/net/ethernet/freescale/fman/inc/ddr_std_ext.h b/drivers/net/ethernet/freescale/fman/inc/ddr_std_ext.h index 69a0025..8bb343fc 100644 --- a/drivers/net/ethernet/freescale/fman/inc/ddr_std_ext.h +++ b/drivers/net/ethernet/freescale/fman/inc/ddr_std_ext.h @@ -56,7 +56,8 @@ typedef enum e_DdrType e_DDR_DDR1, e_DDR_DDR2, e_DDR_DDR3, - e_DDR_DDR3L + e_DDR_DDR3L, + e_DDR_DDR4 } e_DdrType; /**************************************************************************//** diff --git a/drivers/net/ethernet/freescale/fman/inc/flib/fman_common.h b/drivers/net/ethernet/freescale/fman/inc/flib/fman_common.h new file mode 100755 index 0000000..8b194e9 --- /dev/null +++ b/drivers/net/ethernet/freescale/fman/inc/flib/fman_common.h @@ -0,0 +1,78 @@ +/* + * Copyright 2008-2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef __FMAN_COMMON_H +#define __FMAN_COMMON_H + +/**************************************************************************//** + @Description NIA Description +*//***************************************************************************/ +#define NIA_ORDER_RESTOR 0x00800000 +#define NIA_ENG_FM_CTL 0x00000000 +#define NIA_ENG_PRS 0x00440000 +#define NIA_ENG_KG 0x00480000 +#define NIA_ENG_PLCR 0x004C0000 +#define NIA_ENG_BMI 0x00500000 +#define NIA_ENG_QMI_ENQ 0x00540000 +#define NIA_ENG_QMI_DEQ 0x00580000 +#define NIA_ENG_MASK 0x007C0000 + +#define NIA_FM_CTL_AC_CC 0x00000006 +#define NIA_FM_CTL_AC_HC 0x0000000C +#define NIA_FM_CTL_AC_IND_MODE_TX 0x00000008 +#define NIA_FM_CTL_AC_IND_MODE_RX 0x0000000A +#define NIA_FM_CTL_AC_FRAG 0x0000000e +#define NIA_FM_CTL_AC_PRE_FETCH 0x00000010 +#define NIA_FM_CTL_AC_POST_FETCH_PCD 0x00000012 +#define NIA_FM_CTL_AC_POST_FETCH_PCD_UDP_LEN 0x00000018 +#define NIA_FM_CTL_AC_POST_FETCH_NO_PCD 0x00000012 +#define NIA_FM_CTL_AC_FRAG_CHECK 0x00000014 +#define NIA_FM_CTL_AC_PRE_CC 0x00000020 + + +#define NIA_BMI_AC_ENQ_FRAME 0x00000002 +#define NIA_BMI_AC_TX_RELEASE 0x000002C0 +#define NIA_BMI_AC_RELEASE 0x000000C0 +#define NIA_BMI_AC_DISCARD 0x000000C1 +#define NIA_BMI_AC_TX 0x00000274 +#define NIA_BMI_AC_FETCH 0x00000208 +#define NIA_BMI_AC_MASK 0x000003FF + +#define NIA_KG_DIRECT 0x00000100 +#define NIA_KG_CC_EN 0x00000200 +#define NIA_PLCR_ABSOLUTE 0x00008000 + +#define NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA 0x00000202 +#define NIA_BMI_AC_FETCH_ALL_FRAME 0x0000020c + +#endif /* __FMAN_COMMON_H */ diff --git a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_enet.h b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_enet.h index bb0dea9..dde6a4e 100644 --- a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_enet.h +++ b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_enet.h @@ -61,16 +61,212 @@ enum enet_speed { E_ENET_SPEED_10000 = 10000 /**< 10000 Mbps = 10 Gbps */ }; -enum mac_stat_level { - /* No statistics */ - E_MAC_STAT_NONE = 0, - /* Only RMON MIB group 1 (ether stats). Optimized for performance */ - E_MAC_STAT_MIB_GRP1, - /* Only error counters are available. Optimized for performance */ - E_MAC_STAT_PARTIAL, - /* All counters available. Not optimized for performance */ - E_MAC_STAT_FULL +enum mac_type { + E_MAC_DTSEC, + E_MAC_TGEC, + E_MAC_MEMAC }; +/**************************************************************************//** + @Description Enum for inter-module interrupts registration +*//***************************************************************************/ +enum fman_event_modules { + E_FMAN_MOD_PRS, /**< Parser event */ + E_FMAN_MOD_KG, /**< Keygen event */ + E_FMAN_MOD_PLCR, /**< Policer event */ + E_FMAN_MOD_10G_MAC, /**< 10G MAC event */ + E_FMAN_MOD_1G_MAC, /**< 1G MAC event */ + E_FMAN_MOD_TMR, /**< Timer event */ + E_FMAN_MOD_FMAN_CTRL, /**< FMAN Controller Timer event */ + E_FMAN_MOD_MACSEC, + E_FMAN_MOD_DUMMY_LAST +}; + +/**************************************************************************//** + @Description Enum for interrupts types +*//***************************************************************************/ +enum fman_intr_type { + E_FMAN_INTR_TYPE_ERR, + E_FMAN_INTR_TYPE_NORMAL +}; + +/**************************************************************************//** + @Description enum for defining MAC types +*//***************************************************************************/ +enum fman_mac_type { + E_FMAN_MAC_10G = 0, /**< 10G MAC */ + E_FMAN_MAC_1G /**< 1G MAC */ +}; + +enum fman_mac_exceptions { + E_FMAN_MAC_EX_10G_MDIO_SCAN_EVENTMDIO = 0, + /**< 10GEC MDIO scan event interrupt */ + E_FMAN_MAC_EX_10G_MDIO_CMD_CMPL, + /**< 10GEC MDIO command completion interrupt */ + E_FMAN_MAC_EX_10G_REM_FAULT, + /**< 10GEC, mEMAC Remote fault interrupt */ + E_FMAN_MAC_EX_10G_LOC_FAULT, + /**< 10GEC, mEMAC Local fault interrupt */ + E_FMAN_MAC_EX_10G_1TX_ECC_ER, + /**< 10GEC, mEMAC Transmit frame ECC error interrupt */ + E_FMAN_MAC_EX_10G_TX_FIFO_UNFL, + /**< 10GEC, mEMAC Transmit FIFO underflow interrupt */ + E_FMAN_MAC_EX_10G_TX_FIFO_OVFL, + /**< 10GEC, mEMAC Transmit FIFO overflow interrupt */ + E_FMAN_MAC_EX_10G_TX_ER, + /**< 10GEC Transmit frame error interrupt */ + E_FMAN_MAC_EX_10G_RX_FIFO_OVFL, + /**< 10GEC, mEMAC Receive FIFO overflow interrupt */ + E_FMAN_MAC_EX_10G_RX_ECC_ER, + /**< 10GEC, mEMAC Receive frame ECC error interrupt */ + E_FMAN_MAC_EX_10G_RX_JAB_FRM, + /**< 10GEC Receive jabber frame interrupt */ + E_FMAN_MAC_EX_10G_RX_OVRSZ_FRM, + /**< 10GEC Receive oversized frame interrupt */ + E_FMAN_MAC_EX_10G_RX_RUNT_FRM, + /**< 10GEC Receive runt frame interrupt */ + E_FMAN_MAC_EX_10G_RX_FRAG_FRM, + /**< 10GEC Receive fragment frame interrupt */ + E_FMAN_MAC_EX_10G_RX_LEN_ER, + /**< 10GEC Receive payload length error interrupt */ + E_FMAN_MAC_EX_10G_RX_CRC_ER, + /**< 10GEC Receive CRC error interrupt */ + E_FMAN_MAC_EX_10G_RX_ALIGN_ER, + /**< 10GEC Receive alignment error interrupt */ + E_FMAN_MAC_EX_1G_BAB_RX, + /**< dTSEC Babbling receive error */ + E_FMAN_MAC_EX_1G_RX_CTL, + /**< dTSEC Receive control (pause frame) interrupt */ + E_FMAN_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET, + /**< dTSEC Graceful transmit stop complete */ + E_FMAN_MAC_EX_1G_BAB_TX, + /**< dTSEC Babbling transmit error */ + E_FMAN_MAC_EX_1G_TX_CTL, + /**< dTSEC Transmit control (pause frame) interrupt */ + E_FMAN_MAC_EX_1G_TX_ERR, + /**< dTSEC Transmit error */ + E_FMAN_MAC_EX_1G_LATE_COL, + /**< dTSEC Late collision */ + E_FMAN_MAC_EX_1G_COL_RET_LMT, + /**< dTSEC Collision retry limit */ + E_FMAN_MAC_EX_1G_TX_FIFO_UNDRN, + /**< dTSEC Transmit FIFO underrun */ + E_FMAN_MAC_EX_1G_MAG_PCKT, + /**< dTSEC Magic Packet detection */ + E_FMAN_MAC_EX_1G_MII_MNG_RD_COMPLET, + /**< dTSEC MII management read completion */ + E_FMAN_MAC_EX_1G_MII_MNG_WR_COMPLET, + /**< dTSEC MII management write completion */ + E_FMAN_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET, + /**< dTSEC Graceful receive stop complete */ + E_FMAN_MAC_EX_1G_TX_DATA_ERR, + /**< dTSEC Internal data error on transmit */ + E_FMAN_MAC_EX_1G_RX_DATA_ERR, + /**< dTSEC Internal data error on receive */ + E_FMAN_MAC_EX_1G_1588_TS_RX_ERR, + /**< dTSEC Time-Stamp Receive Error */ + E_FMAN_MAC_EX_1G_RX_MIB_CNT_OVFL, + /**< dTSEC MIB counter overflow */ + E_FMAN_MAC_EX_TS_FIFO_ECC_ERR, + /**< mEMAC Time-stamp FIFO ECC error interrupt; + not supported on T4240/B4860 rev1 chips */ +}; + +#define ENET_IF_SGMII_BASEX 0x80000000 + /**< SGMII/QSGII interface with 1000BaseX auto-negotiation between MAC + and phy or backplane; + Note: 1000BaseX auto-negotiation relates only to interface between MAC + and phy/backplane, SGMII phy can still synchronize with far-end phy at + 10Mbps, 100Mbps or 1000Mbps */ + +enum enet_mode { + E_ENET_MODE_INVALID = 0, + /**< Invalid Ethernet mode */ + E_ENET_MODE_MII_10 = (E_ENET_IF_MII | E_ENET_SPEED_10), + /**< 10 Mbps MII */ + E_ENET_MODE_MII_100 = (E_ENET_IF_MII | E_ENET_SPEED_100), + /**< 100 Mbps MII */ + E_ENET_MODE_RMII_10 = (E_ENET_IF_RMII | E_ENET_SPEED_10), + /**< 10 Mbps RMII */ + E_ENET_MODE_RMII_100 = (E_ENET_IF_RMII | E_ENET_SPEED_100), + /**< 100 Mbps RMII */ + E_ENET_MODE_SMII_10 = (E_ENET_IF_SMII | E_ENET_SPEED_10), + /**< 10 Mbps SMII */ + E_ENET_MODE_SMII_100 = (E_ENET_IF_SMII | E_ENET_SPEED_100), + /**< 100 Mbps SMII */ + E_ENET_MODE_GMII_1000 = (E_ENET_IF_GMII | E_ENET_SPEED_1000), + /**< 1000 Mbps GMII */ + E_ENET_MODE_RGMII_10 = (E_ENET_IF_RGMII | E_ENET_SPEED_10), + /**< 10 Mbps RGMII */ + E_ENET_MODE_RGMII_100 = (E_ENET_IF_RGMII | E_ENET_SPEED_100), + /**< 100 Mbps RGMII */ + E_ENET_MODE_RGMII_1000 = (E_ENET_IF_RGMII | E_ENET_SPEED_1000), + /**< 1000 Mbps RGMII */ + E_ENET_MODE_TBI_1000 = (E_ENET_IF_TBI | E_ENET_SPEED_1000), + /**< 1000 Mbps TBI */ + E_ENET_MODE_RTBI_1000 = (E_ENET_IF_RTBI | E_ENET_SPEED_1000), + /**< 1000 Mbps RTBI */ + E_ENET_MODE_SGMII_10 = (E_ENET_IF_SGMII | E_ENET_SPEED_10), + /**< 10 Mbps SGMII with auto-negotiation between MAC and + SGMII phy according to Cisco SGMII specification */ + E_ENET_MODE_SGMII_100 = (E_ENET_IF_SGMII | E_ENET_SPEED_100), + /**< 100 Mbps SGMII with auto-negotiation between MAC and + SGMII phy according to Cisco SGMII specification */ + E_ENET_MODE_SGMII_1000 = (E_ENET_IF_SGMII | E_ENET_SPEED_1000), + /**< 1000 Mbps SGMII with auto-negotiation between MAC and + SGMII phy according to Cisco SGMII specification */ + E_ENET_MODE_SGMII_BASEX_10 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII + | E_ENET_SPEED_10), + /**< 10 Mbps SGMII with 1000BaseX auto-negotiation between + MAC and SGMII phy or backplane */ + E_ENET_MODE_SGMII_BASEX_100 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII + | E_ENET_SPEED_100), + /**< 100 Mbps SGMII with 1000BaseX auto-negotiation between + MAC and SGMII phy or backplane */ + E_ENET_MODE_SGMII_BASEX_1000 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII + | E_ENET_SPEED_1000), + /**< 1000 Mbps SGMII with 1000BaseX auto-negotiation between + MAC and SGMII phy or backplane */ + E_ENET_MODE_QSGMII_1000 = (E_ENET_IF_QSGMII | E_ENET_SPEED_1000), + /**< 1000 Mbps QSGMII with auto-negotiation between MAC and + QSGMII phy according to Cisco QSGMII specification */ + E_ENET_MODE_QSGMII_BASEX_1000 = (ENET_IF_SGMII_BASEX | E_ENET_IF_QSGMII + | E_ENET_SPEED_1000), + /**< 1000 Mbps QSGMII with 1000BaseX auto-negotiation between + MAC and QSGMII phy or backplane */ + E_ENET_MODE_XGMII_10000 = (E_ENET_IF_XGMII | E_ENET_SPEED_10000), + /**< 10000 Mbps XGMII */ + E_ENET_MODE_XFI_10000 = (E_ENET_IF_XFI | E_ENET_SPEED_10000) + /**< 10000 Mbps XFI */ +}; + +enum fmam_mac_statistics_level { + E_FMAN_MAC_NONE_STATISTICS, /**< No statistics */ + E_FMAN_MAC_PARTIAL_STATISTICS, /**< Only error counters are available; + Optimized for performance */ + E_FMAN_MAC_FULL_STATISTICS /**< All counters available; Not + optimized for performance */ +}; + +#define _MAKE_ENET_MODE(_interface, _speed) (enum enet_mode)((_interface) \ + | (_speed)) + +#define _ENET_INTERFACE_FROM_MODE(mode) (enum enet_interface) \ + ((mode) & 0x0FFF0000) +#define _ENET_SPEED_FROM_MODE(mode) (enum enet_speed)((mode) & 0x0000FFFF) +#define _ENET_ADDR_TO_UINT64(_enet_addr) \ + (uint64_t)(((uint64_t)(_enet_addr)[0] << 40) | \ + ((uint64_t)(_enet_addr)[1] << 32) | \ + ((uint64_t)(_enet_addr)[2] << 24) | \ + ((uint64_t)(_enet_addr)[3] << 16) | \ + ((uint64_t)(_enet_addr)[4] << 8) | \ + ((uint64_t)(_enet_addr)[5])) + +#define _MAKE_ENET_ADDR_FROM_UINT64(_addr64, _enet_addr) \ + do { \ + int i; \ + for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++) \ + (_enet_addr)[i] = (uint8_t)((_addr64) >> ((5-i)*8));\ + } while (0) #endif /* __FSL_ENET_H */ diff --git a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman.h b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman.h index 2933f75..e66ad73 100755 --- a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman.h +++ b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman.h @@ -35,7 +35,6 @@ #include "common/general.h" - struct fman_ext_pool_params { uint8_t id; /**< External buffer pool id */ uint16_t size; /**< External buffer pool buffer size */ @@ -109,6 +108,11 @@ typedef struct t_FmPrsResult fm_prs_result_t; typedef enum e_EnetMode enet_mode_t; typedef t_Handle handle_t; +struct fman_revision_info { + uint8_t majorRev; /**< Major revision */ + uint8_t minorRev; /**< Minor revision */ +}; + /* sizes */ #define CAPWAP_FRAG_EXTRA_SPACE 32 #define OFFSET_UNITS 16 @@ -117,5 +121,706 @@ typedef t_Handle handle_t; #define MAX_EXT_OFFSET 496 #define MAX_EXT_BUFFER_OFFSET 511 +/************************************************************************** + @Description Memory Mapped Registers +***************************************************************************/ +#define FMAN_LIODN_TBL 64 /* size of LIODN table */ + +struct fman_fpm_regs { + uint32_t fmfp_tnc; /**< FPM TNUM Control 0x00 */ + uint32_t fmfp_prc; /**< FPM Port_ID FmCtl Association 0x04 */ + uint32_t fmfp_brkc; /**< FPM Breakpoint Control 0x08 */ + uint32_t fmfp_mxd; /**< FPM Flush Control 0x0c */ + uint32_t fmfp_dist1; /**< FPM Dispatch Thresholds1 0x10 */ + uint32_t fmfp_dist2; /**< FPM Dispatch Thresholds2 0x14 */ + uint32_t fm_epi; /**< FM Error Pending Interrupts 0x18 */ + uint32_t fm_rie; /**< FM Error Interrupt Enable 0x1c */ + uint32_t fmfp_fcev[4]; /**< FPM FMan-Controller Event 1-4 0x20-0x2f */ + uint32_t res0030[4]; /**< res 0x30 - 0x3f */ + uint32_t fmfp_cee[4]; /**< PM FMan-Controller Event 1-4 0x40-0x4f */ + uint32_t res0050[4]; /**< res 0x50-0x5f */ + uint32_t fmfp_tsc1; /**< FPM TimeStamp Control1 0x60 */ + uint32_t fmfp_tsc2; /**< FPM TimeStamp Control2 0x64 */ + uint32_t fmfp_tsp; /**< FPM Time Stamp 0x68 */ + uint32_t fmfp_tsf; /**< FPM Time Stamp Fraction 0x6c */ + uint32_t fm_rcr; /**< FM Rams Control 0x70 */ + uint32_t fmfp_extc; /**< FPM External Requests Control 0x74 */ + uint32_t fmfp_ext1; /**< FPM External Requests Config1 0x78 */ + uint32_t fmfp_ext2; /**< FPM External Requests Config2 0x7c */ + uint32_t fmfp_drd[16]; /**< FPM Data_Ram Data 0-15 0x80 - 0xbf */ + uint32_t fmfp_dra; /**< FPM Data Ram Access 0xc0 */ + uint32_t fm_ip_rev_1; /**< FM IP Block Revision 1 0xc4 */ + uint32_t fm_ip_rev_2; /**< FM IP Block Revision 2 0xc8 */ + uint32_t fm_rstc; /**< FM Reset Command 0xcc */ + uint32_t fm_cld; /**< FM Classifier Debug 0xd0 */ + uint32_t fm_npi; /**< FM Normal Pending Interrupts 0xd4 */ + uint32_t fmfp_exte; /**< FPM External Requests Enable 0xd8 */ + uint32_t fmfp_ee; /**< FPM Event & Mask 0xdc */ + uint32_t fmfp_cev[4]; /**< FPM CPU Event 1-4 0xe0-0xef */ + uint32_t res00f0[4]; /**< res 0xf0-0xff */ + uint32_t fmfp_ps[50]; /**< FPM Port Status 0x100-0x1c7 */ + uint32_t res01c8[14]; /**< res 0x1c8-0x1ff */ + uint32_t fmfp_clfabc; /**< FPM CLFABC 0x200 */ + uint32_t fmfp_clfcc; /**< FPM CLFCC 0x204 */ + uint32_t fmfp_clfaval; /**< FPM CLFAVAL 0x208 */ + uint32_t fmfp_clfbval; /**< FPM CLFBVAL 0x20c */ + uint32_t fmfp_clfcval; /**< FPM CLFCVAL 0x210 */ + uint32_t fmfp_clfamsk; /**< FPM CLFAMSK 0x214 */ + uint32_t fmfp_clfbmsk; /**< FPM CLFBMSK 0x218 */ + uint32_t fmfp_clfcmsk; /**< FPM CLFCMSK 0x21c */ + uint32_t fmfp_clfamc; /**< FPM CLFAMC 0x220 */ + uint32_t fmfp_clfbmc; /**< FPM CLFBMC 0x224 */ + uint32_t fmfp_clfcmc; /**< FPM CLFCMC 0x228 */ + uint32_t fmfp_decceh; /**< FPM DECCEH 0x22c */ + uint32_t res0230[116]; /**< res 0x230 - 0x3ff */ + uint32_t fmfp_ts[128]; /**< 0x400: FPM Task Status 0x400 - 0x5ff */ + uint32_t res0600[0x400 - 384]; +}; + +struct fman_bmi_regs { + uint32_t fmbm_init; /**< BMI Initialization 0x00 */ + uint32_t fmbm_cfg1; /**< BMI Configuration 1 0x04 */ + uint32_t fmbm_cfg2; /**< BMI Configuration 2 0x08 */ + uint32_t res000c[5]; /**< 0x0c - 0x1f */ + uint32_t fmbm_ievr; /**< Interrupt Event Register 0x20 */ + uint32_t fmbm_ier; /**< Interrupt Enable Register 0x24 */ + uint32_t fmbm_ifr; /**< Interrupt Force Register 0x28 */ + uint32_t res002c[5]; /**< 0x2c - 0x3f */ + uint32_t fmbm_arb[8]; /**< BMI Arbitration 0x40 - 0x5f */ + uint32_t res0060[12]; /**<0x60 - 0x8f */ + uint32_t fmbm_dtc[3]; /**< Debug Trap Counter 0x90 - 0x9b */ + uint32_t res009c; /**< 0x9c */ + uint32_t fmbm_dcv[3][4]; /**< Debug Compare val 0xa0-0xcf */ + uint32_t fmbm_dcm[3][4]; /**< Debug Compare Mask 0xd0-0xff */ + uint32_t fmbm_gde; /**< BMI Global Debug Enable 0x100 */ + uint32_t fmbm_pp[63]; /**< BMI Port Parameters 0x104 - 0x1ff */ + uint32_t res0200; /**< 0x200 */ + uint32_t fmbm_pfs[63]; /**< BMI Port FIFO Size 0x204 - 0x2ff */ + uint32_t res0300; /**< 0x300 */ + uint32_t fmbm_spliodn[63]; /**< Port Partition ID 0x304 - 0x3ff */ +}; + +struct fman_qmi_regs { + uint32_t fmqm_gc; /**< General Configuration Register 0x00 */ + uint32_t res0004; /**< 0x04 */ + uint32_t fmqm_eie; /**< Error Interrupt Event Register 0x08 */ + uint32_t fmqm_eien; /**< Error Interrupt Enable Register 0x0c */ + uint32_t fmqm_eif; /**< Error Interrupt Force Register 0x10 */ + uint32_t fmqm_ie; /**< Interrupt Event Register 0x14 */ + uint32_t fmqm_ien; /**< Interrupt Enable Register 0x18 */ + uint32_t fmqm_if; /**< Interrupt Force Register 0x1c */ + uint32_t fmqm_gs; /**< Global Status Register 0x20 */ + uint32_t fmqm_ts; /**< Task Status Register 0x24 */ + uint32_t fmqm_etfc; /**< Enqueue Total Frame Counter 0x28 */ + uint32_t fmqm_dtfc; /**< Dequeue Total Frame Counter 0x2c */ + uint32_t fmqm_dc0; /**< Dequeue Counter 0 0x30 */ + uint32_t fmqm_dc1; /**< Dequeue Counter 1 0x34 */ + uint32_t fmqm_dc2; /**< Dequeue Counter 2 0x38 */ + uint32_t fmqm_dc3; /**< Dequeue Counter 3 0x3c */ + uint32_t fmqm_dfdc; /**< Dequeue FQID from Default Counter 0x40 */ + uint32_t fmqm_dfcc; /**< Dequeue FQID from Context Counter 0x44 */ + uint32_t fmqm_dffc; /**< Dequeue FQID from FD Counter 0x48 */ + uint32_t fmqm_dcc; /**< Dequeue Confirm Counter 0x4c */ + uint32_t res0050[7]; /**< 0x50 - 0x6b */ + uint32_t fmqm_tapc; /**< Tnum Aging Period Control 0x6c */ + uint32_t fmqm_dmcvc; /**< Dequeue MAC Command Valid Counter 0x70 */ + uint32_t fmqm_difdcc; /**< Dequeue Invalid FD Command Counter 0x74 */ + uint32_t fmqm_da1v; /**< Dequeue A1 Valid Counter 0x78 */ + uint32_t res007c; /**< 0x7c */ + uint32_t fmqm_dtc; /**< 0x80 Debug Trap Counter 0x80 */ + uint32_t fmqm_efddd; /**< 0x84 Enqueue Frame desc Dynamic dbg 0x84 */ + uint32_t res0088[2]; /**< 0x88 - 0x8f */ + struct { + uint32_t fmqm_dtcfg1; /**< 0x90 dbg trap cfg 1 Register 0x00 */ + uint32_t fmqm_dtval1; /**< Debug Trap Value 1 Register 0x04 */ + uint32_t fmqm_dtm1; /**< Debug Trap Mask 1 Register 0x08 */ + uint32_t fmqm_dtc1; /**< Debug Trap Counter 1 Register 0x0c */ + uint32_t fmqm_dtcfg2; /**< dbg Trap cfg 2 Register 0x10 */ + uint32_t fmqm_dtval2; /**< Debug Trap Value 2 Register 0x14 */ + uint32_t fmqm_dtm2; /**< Debug Trap Mask 2 Register 0x18 */ + uint32_t res001c; /**< 0x1c */ + } dbg_traps[3]; /**< 0x90 - 0xef */ + uint8_t res00f0[0x400 - 0xf0]; /**< 0xf0 - 0x3ff */ +}; + +struct fman_dma_regs { + uint32_t fmdmsr; /**< FM DMA status register 0x00 */ + uint32_t fmdmmr; /**< FM DMA mode register 0x04 */ + uint32_t fmdmtr; /**< FM DMA bus threshold register 0x08 */ + uint32_t fmdmhy; /**< FM DMA bus hysteresis register 0x0c */ + uint32_t fmdmsetr; /**< FM DMA SOS emergency Threshold Register 0x10 */ + uint32_t fmdmtah; /**< FM DMA transfer bus address high reg 0x14 */ + uint32_t fmdmtal; /**< FM DMA transfer bus address low reg 0x18 */ + uint32_t fmdmtcid; /**< FM DMA transfer bus communication ID reg 0x1c */ + uint32_t fmdmra; /**< FM DMA bus internal ram address register 0x20 */ + uint32_t fmdmrd; /**< FM DMA bus internal ram data register 0x24 */ + uint32_t fmdmwcr; /**< FM DMA CAM watchdog counter value 0x28 */ + uint32_t fmdmebcr; /**< FM DMA CAM base in MURAM register 0x2c */ + uint32_t fmdmccqdr; /**< FM DMA CAM and CMD Queue Debug reg 0x30 */ + uint32_t fmdmccqvr1; /**< FM DMA CAM and CMD Queue Value reg #1 0x34 */ + uint32_t fmdmccqvr2; /**< FM DMA CAM and CMD Queue Value reg #2 0x38 */ + uint32_t fmdmcqvr3; /**< FM DMA CMD Queue Value register #3 0x3c */ + uint32_t fmdmcqvr4; /**< FM DMA CMD Queue Value register #4 0x40 */ + uint32_t fmdmcqvr5; /**< FM DMA CMD Queue Value register #5 0x44 */ + uint32_t fmdmsefrc; /**< FM DMA Semaphore Entry Full Reject Cntr 0x48 */ + uint32_t fmdmsqfrc; /**< FM DMA Semaphore Queue Full Reject Cntr 0x4c */ + uint32_t fmdmssrc; /**< FM DMA Semaphore SYNC Reject Counter 0x50 */ + uint32_t fmdmdcr; /**< FM DMA Debug Counter 0x54 */ + uint32_t fmdmemsr; /**< FM DMA Emergency Smoother Register 0x58 */ + uint32_t res005c; /**< 0x5c */ + uint32_t fmdmplr[FMAN_LIODN_TBL / 2]; /**< DMA LIODN regs 0x60-0xdf */ + uint32_t res00e0[0x400 - 56]; +}; + +struct fman_rg { + struct fman_fpm_regs *fpm_rg; + struct fman_dma_regs *dma_rg; + struct fman_bmi_regs *bmi_rg; + struct fman_qmi_regs *qmi_rg; +}; + +enum fman_dma_cache_override { + E_FMAN_DMA_NO_CACHE_OR = 0, /**< No override of the Cache field */ + E_FMAN_DMA_NO_STASH_DATA, /**< No data stashing in system level cache */ + E_FMAN_DMA_MAY_STASH_DATA, /**< Stashing allowed in sys level cache */ + E_FMAN_DMA_STASH_DATA /**< Stashing performed in system level cache */ +}; + +enum fman_dma_aid_mode { + E_FMAN_DMA_AID_OUT_PORT_ID = 0, /**< 4 LSB of PORT_ID */ + E_FMAN_DMA_AID_OUT_TNUM /**< 4 LSB of TNUM */ +}; + +enum fman_dma_dbg_cnt_mode { + E_FMAN_DMA_DBG_NO_CNT = 0, /**< No counting */ + E_FMAN_DMA_DBG_CNT_DONE, /**< Count DONE commands */ + E_FMAN_DMA_DBG_CNT_COMM_Q_EM, /**< command Q emergency signal */ + E_FMAN_DMA_DBG_CNT_INT_READ_EM, /**< Read buf emergency signal */ + E_FMAN_DMA_DBG_CNT_INT_WRITE_EM, /**< Write buf emergency signal */ + E_FMAN_DMA_DBG_CNT_FPM_WAIT, /**< FPM WAIT signal */ + E_FMAN_DMA_DBG_CNT_SIGLE_BIT_ECC, /**< Single bit ECC errors */ + E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT /**< RAW & WAR protection counter */ +}; + +enum fman_dma_emergency_level { + E_FMAN_DMA_EM_EBS = 0, /**< EBS emergency */ + E_FMAN_DMA_EM_SOS /**< SOS emergency */ +}; + +enum fman_catastrophic_err { + E_FMAN_CATAST_ERR_STALL_PORT = 0, /**< Port_ID stalled reset required */ + E_FMAN_CATAST_ERR_STALL_TASK /**< Only erroneous task is stalled */ +}; + +enum fman_dma_err { + E_FMAN_DMA_ERR_CATASTROPHIC = 0, /**< Catastrophic DMA error */ + E_FMAN_DMA_ERR_REPORT /**< Reported DMA error */ +}; + +struct fman_cfg { + uint16_t liodn_bs_pr_port[FMAN_LIODN_TBL];/* base per port */ + bool en_counters; + uint8_t disp_limit_tsh; + uint8_t prs_disp_tsh; + uint8_t plcr_disp_tsh; + uint8_t kg_disp_tsh; + uint8_t bmi_disp_tsh; + uint8_t qmi_enq_disp_tsh; + uint8_t qmi_deq_disp_tsh; + uint8_t fm_ctl1_disp_tsh; + uint8_t fm_ctl2_disp_tsh; + enum fman_dma_cache_override dma_cache_override; + enum fman_dma_aid_mode dma_aid_mode; + bool dma_aid_override; + uint8_t dma_axi_dbg_num_of_beats; + uint8_t dma_cam_num_of_entries; + uint32_t dma_watchdog; + uint8_t dma_comm_qtsh_asrt_emer; + uint8_t dma_write_buf_tsh_asrt_emer; + uint8_t dma_read_buf_tsh_asrt_emer; + uint8_t dma_comm_qtsh_clr_emer; + uint8_t dma_write_buf_tsh_clr_emer; + uint8_t dma_read_buf_tsh_clr_emer; + uint32_t dma_sos_emergency; + enum fman_dma_dbg_cnt_mode dma_dbg_cnt_mode; + bool dma_stop_on_bus_error; + bool dma_en_emergency; + uint32_t dma_emergency_bus_select; + enum fman_dma_emergency_level dma_emergency_level; + bool dma_en_emergency_smoother; + uint32_t dma_emergency_switch_counter; + bool halt_on_external_activ; + bool halt_on_unrecov_ecc_err; + enum fman_catastrophic_err catastrophic_err; + enum fman_dma_err dma_err; + bool en_muram_test_mode; + bool en_iram_test_mode; + bool external_ecc_rams_enable; + uint16_t tnum_aging_period; + uint32_t exceptions; + uint16_t clk_freq; + bool pedantic_dma; + uint32_t cam_base_addr; + uint32_t fifo_base_addr; + uint32_t total_fifo_size; + uint8_t total_num_of_tasks; + bool qmi_deq_option_support; + uint32_t qmi_def_tnums_thresh; + bool fman_partition_array; + uint8_t num_of_fman_ctrl_evnt_regs; +}; + +/**************************************************************************//** + @Description Exceptions +*//***************************************************************************/ +#define FMAN_EX_DMA_BUS_ERROR 0x80000000 +#define FMAN_EX_DMA_READ_ECC 0x40000000 +#define FMAN_EX_DMA_SYSTEM_WRITE_ECC 0x20000000 +#define FMAN_EX_DMA_FM_WRITE_ECC 0x10000000 +#define FMAN_EX_FPM_STALL_ON_TASKS 0x08000000 +#define FMAN_EX_FPM_SINGLE_ECC 0x04000000 +#define FMAN_EX_FPM_DOUBLE_ECC 0x02000000 +#define FMAN_EX_QMI_SINGLE_ECC 0x01000000 +#define FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 +#define FMAN_EX_QMI_DOUBLE_ECC 0x00400000 +#define FMAN_EX_BMI_LIST_RAM_ECC 0x00200000 +#define FMAN_EX_BMI_PIPELINE_ECC 0x00100000 +#define FMAN_EX_BMI_STATISTICS_RAM_ECC 0x00080000 +#define FMAN_EX_IRAM_ECC 0x00040000 +#define FMAN_EX_NURAM_ECC 0x00020000 +#define FMAN_EX_BMI_DISPATCH_RAM_ECC 0x00010000 + +enum fman_exceptions { + E_FMAN_EX_DMA_BUS_ERROR = 0, /**< DMA bus error. */ + E_FMAN_EX_DMA_READ_ECC, /**< Read Buffer ECC error */ + E_FMAN_EX_DMA_SYSTEM_WRITE_ECC, /**< Write Buffer ECC err on sys side */ + E_FMAN_EX_DMA_FM_WRITE_ECC, /**< Write Buffer ECC error on FM side */ + E_FMAN_EX_FPM_STALL_ON_TASKS, /**< Stall of tasks on FPM */ + E_FMAN_EX_FPM_SINGLE_ECC, /**< Single ECC on FPM. */ + E_FMAN_EX_FPM_DOUBLE_ECC, /**< Double ECC error on FPM ram access */ + E_FMAN_EX_QMI_SINGLE_ECC, /**< Single ECC on QMI. */ + E_FMAN_EX_QMI_DOUBLE_ECC, /**< Double bit ECC occurred on QMI */ + E_FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID,/**< DeQ from unknown port id */ + E_FMAN_EX_BMI_LIST_RAM_ECC, /**< Linked List RAM ECC error */ + E_FMAN_EX_BMI_STORAGE_PROFILE_ECC, /**< storage profile */ + E_FMAN_EX_BMI_STATISTICS_RAM_ECC, /**< Statistics RAM ECC Err Enable */ + E_FMAN_EX_BMI_DISPATCH_RAM_ECC, /**< Dispatch RAM ECC Error Enable */ + E_FMAN_EX_IRAM_ECC, /**< Double bit ECC occurred on IRAM*/ + E_FMAN_EX_MURAM_ECC /**< Double bit ECC occurred on MURAM*/ +}; + +enum fman_counters { + E_FMAN_COUNTERS_ENQ_TOTAL_FRAME = 0, /**< QMI tot enQ frames counter */ + E_FMAN_COUNTERS_DEQ_TOTAL_FRAME, /**< QMI tot deQ frames counter */ + E_FMAN_COUNTERS_DEQ_0, /**< QMI 0 frames from QMan counter */ + E_FMAN_COUNTERS_DEQ_1, /**< QMI 1 frames from QMan counter */ + E_FMAN_COUNTERS_DEQ_2, /**< QMI 2 frames from QMan counter */ + E_FMAN_COUNTERS_DEQ_3, /**< QMI 3 frames from QMan counter */ + E_FMAN_COUNTERS_DEQ_FROM_DEFAULT, /**< QMI deQ from dflt queue cntr */ + E_FMAN_COUNTERS_DEQ_FROM_CONTEXT, /**< QMI deQ from FQ context cntr */ + E_FMAN_COUNTERS_DEQ_FROM_FD, /**< QMI deQ from FD command field cntr */ + E_FMAN_COUNTERS_DEQ_CONFIRM, /**< QMI dequeue confirm counter */ + E_FMAN_COUNTERS_SEMAPHOR_ENTRY_FULL_REJECT, /**< DMA full entry cntr */ + E_FMAN_COUNTERS_SEMAPHOR_QUEUE_FULL_REJECT, /**< DMA full CAM Q cntr */ + E_FMAN_COUNTERS_SEMAPHOR_SYNC_REJECT /**< DMA sync counter */ +}; + +#define FPM_PRT_FM_CTL1 0x00000001 +#define FPM_PRT_FM_CTL2 0x00000002 + +/**************************************************************************//** + @Description DMA definitions +*//***************************************************************************/ + +/* masks */ +#define DMA_MODE_AID_OR 0x20000000 +#define DMA_MODE_SBER 0x10000000 +#define DMA_MODE_BER 0x00200000 +#define DMA_MODE_EB 0x00100000 +#define DMA_MODE_ECC 0x00000020 +#define DMA_MODE_PRIVILEGE_PROT 0x00001000 +#define DMA_MODE_SECURE_PROT 0x00000800 +#define DMA_MODE_EMER_READ 0x00080000 +#define DMA_MODE_EMER_WRITE 0x00040000 +#define DMA_MODE_CACHE_OR_MASK 0xC0000000 +#define DMA_MODE_CEN_MASK 0x0000E000 +#define DMA_MODE_DBG_MASK 0x00000380 +#define DMA_MODE_AXI_DBG_MASK 0x0F000000 + +#define DMA_EMSR_EMSTR_MASK 0x0000FFFF + +#define DMA_TRANSFER_PORTID_MASK 0xFF000000 +#define DMA_TRANSFER_TNUM_MASK 0x00FF0000 +#define DMA_TRANSFER_LIODN_MASK 0x00000FFF + +#define DMA_HIGH_LIODN_MASK 0x0FFF0000 +#define DMA_LOW_LIODN_MASK 0x00000FFF + +#define DMA_STATUS_CMD_QUEUE_NOT_EMPTY 0x10000000 +#define DMA_STATUS_BUS_ERR 0x08000000 +#define DMA_STATUS_READ_ECC 0x04000000 +#define DMA_STATUS_SYSTEM_WRITE_ECC 0x02000000 +#define DMA_STATUS_FM_WRITE_ECC 0x01000000 +#define DMA_STATUS_SYSTEM_DPEXT_ECC 0x00800000 +#define DMA_STATUS_FM_DPEXT_ECC 0x00400000 +#define DMA_STATUS_SYSTEM_DPDAT_ECC 0x00200000 +#define DMA_STATUS_FM_DPDAT_ECC 0x00100000 +#define DMA_STATUS_FM_SPDAT_ECC 0x00080000 + +#define FM_LIODN_BASE_MASK 0x00000FFF + +/* shifts */ +#define DMA_MODE_CACHE_OR_SHIFT 30 +#define DMA_MODE_BUS_PRI_SHIFT 16 +#define DMA_MODE_AXI_DBG_SHIFT 24 +#define DMA_MODE_CEN_SHIFT 13 +#define DMA_MODE_BUS_PROT_SHIFT 10 +#define DMA_MODE_DBG_SHIFT 7 +#define DMA_MODE_EMER_LVL_SHIFT 6 +#define DMA_MODE_AID_MODE_SHIFT 4 +#define DMA_MODE_MAX_AXI_DBG_NUM_OF_BEATS 16 +#define DMA_MODE_MAX_CAM_NUM_OF_ENTRIES 32 + +#define DMA_THRESH_COMMQ_SHIFT 24 +#define DMA_THRESH_READ_INT_BUF_SHIFT 16 + +#define DMA_LIODN_SHIFT 16 + +#define DMA_TRANSFER_PORTID_SHIFT 24 +#define DMA_TRANSFER_TNUM_SHIFT 16 + +/* sizes */ +#define DMA_MAX_WATCHDOG 0xffffffff + +/* others */ +#define DMA_CAM_SIZEOF_ENTRY 0x40 +#define DMA_CAM_ALIGN 0x1000 +#define DMA_CAM_UNITS 8 + +/**************************************************************************//** + @Description General defines +*//***************************************************************************/ + +#define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL +#define FM_UCODE_DEBUG_INSTRUCTION 0x6ffff805UL + +/**************************************************************************//** + @Description FPM defines +*//***************************************************************************/ + +/* masks */ +#define FPM_EV_MASK_DOUBLE_ECC 0x80000000 +#define FPM_EV_MASK_STALL 0x40000000 +#define FPM_EV_MASK_SINGLE_ECC 0x20000000 +#define FPM_EV_MASK_RELEASE_FM 0x00010000 +#define FPM_EV_MASK_DOUBLE_ECC_EN 0x00008000 +#define FPM_EV_MASK_STALL_EN 0x00004000 +#define FPM_EV_MASK_SINGLE_ECC_EN 0x00002000 +#define FPM_EV_MASK_EXTERNAL_HALT 0x00000008 +#define FPM_EV_MASK_ECC_ERR_HALT 0x00000004 + +#define FPM_RAM_RAMS_ECC_EN 0x80000000 +#define FPM_RAM_IRAM_ECC_EN 0x40000000 +#define FPM_RAM_MURAM_ECC 0x00008000 +#define FPM_RAM_IRAM_ECC 0x00004000 +#define FPM_RAM_MURAM_TEST_ECC 0x20000000 +#define FPM_RAM_IRAM_TEST_ECC 0x10000000 +#define FPM_RAM_RAMS_ECC_EN_SRC_SEL 0x08000000 + +#define FPM_IRAM_ECC_ERR_EX_EN 0x00020000 +#define FPM_MURAM_ECC_ERR_EX_EN 0x00040000 + +#define FPM_REV1_MAJOR_MASK 0x0000FF00 +#define FPM_REV1_MINOR_MASK 0x000000FF + +#define FPM_REV2_INTEG_MASK 0x00FF0000 +#define FPM_REV2_ERR_MASK 0x0000FF00 +#define FPM_REV2_CFG_MASK 0x000000FF + +#define FPM_TS_FRACTION_MASK 0x0000FFFF +#define FPM_TS_CTL_EN 0x80000000 + +#define FPM_PRC_REALSE_STALLED 0x00800000 + +#define FPM_PS_STALLED 0x00800000 +#define FPM_PS_FM_CTL1_SEL 0x80000000 +#define FPM_PS_FM_CTL2_SEL 0x40000000 +#define FPM_PS_FM_CTL_SEL_MASK (FPM_PS_FM_CTL1_SEL | FPM_PS_FM_CTL2_SEL) + +#define FPM_RSTC_FM_RESET 0x80000000 +#define FPM_RSTC_10G0_RESET 0x04000000 +#define FPM_RSTC_1G0_RESET 0x40000000 +#define FPM_RSTC_1G1_RESET 0x20000000 +#define FPM_RSTC_1G2_RESET 0x10000000 +#define FPM_RSTC_1G3_RESET 0x08000000 +#define FPM_RSTC_1G4_RESET 0x02000000 + + +#define FPM_DISP_LIMIT_MASK 0x1F000000 +#define FPM_THR1_PRS_MASK 0xFF000000 +#define FPM_THR1_KG_MASK 0x00FF0000 +#define FPM_THR1_PLCR_MASK 0x0000FF00 +#define FPM_THR1_BMI_MASK 0x000000FF + +#define FPM_THR2_QMI_ENQ_MASK 0xFF000000 +#define FPM_THR2_QMI_DEQ_MASK 0x000000FF +#define FPM_THR2_FM_CTL1_MASK 0x00FF0000 +#define FPM_THR2_FM_CTL2_MASK 0x0000FF00 + +/* shifts */ +#define FPM_DISP_LIMIT_SHIFT 24 + +#define FPM_THR1_PRS_SHIFT 24 +#define FPM_THR1_KG_SHIFT 16 +#define FPM_THR1_PLCR_SHIFT 8 +#define FPM_THR1_BMI_SHIFT 0 + +#define FPM_THR2_QMI_ENQ_SHIFT 24 +#define FPM_THR2_QMI_DEQ_SHIFT 0 +#define FPM_THR2_FM_CTL1_SHIFT 16 +#define FPM_THR2_FM_CTL2_SHIFT 8 + +#define FPM_EV_MASK_CAT_ERR_SHIFT 1 +#define FPM_EV_MASK_DMA_ERR_SHIFT 0 + +#define FPM_REV1_MAJOR_SHIFT 8 +#define FPM_REV1_MINOR_SHIFT 0 + +#define FPM_REV2_INTEG_SHIFT 16 +#define FPM_REV2_ERR_SHIFT 8 +#define FPM_REV2_CFG_SHIFT 0 + +#define FPM_TS_INT_SHIFT 16 + +#define FPM_PORT_FM_CTL_PORTID_SHIFT 24 + +#define FPM_PS_FM_CTL_SEL_SHIFT 30 +#define FPM_PRC_ORA_FM_CTL_SEL_SHIFT 16 + +#define FPM_DISP_LIMIT_SHIFT 24 + +/* Interrupts defines */ +#define FPM_EVENT_FM_CTL_0 0x00008000 +#define FPM_EVENT_FM_CTL 0x0000FF00 +#define FPM_EVENT_FM_CTL_BRK 0x00000080 + +/* others */ +#define FPM_MAX_DISP_LIMIT 31 +#define FPM_RSTC_FM_RESET 0x80000000 +#define FPM_RSTC_1G0_RESET 0x40000000 +#define FPM_RSTC_1G1_RESET 0x20000000 +#define FPM_RSTC_1G2_RESET 0x10000000 +#define FPM_RSTC_1G3_RESET 0x08000000 +#define FPM_RSTC_10G0_RESET 0x04000000 +#define FPM_RSTC_1G4_RESET 0x02000000 +#define FPM_RSTC_1G5_RESET 0x01000000 +#define FPM_RSTC_1G6_RESET 0x00800000 +#define FPM_RSTC_1G7_RESET 0x00400000 +#define FPM_RSTC_10G1_RESET 0x00200000 +/**************************************************************************//** + @Description BMI defines +*//***************************************************************************/ +/* masks */ +#define BMI_INIT_START 0x80000000 +#define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000 +#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000 +#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000 +#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000 +#define BMI_NUM_OF_TASKS_MASK 0x3F000000 +#define BMI_NUM_OF_EXTRA_TASKS_MASK 0x000F0000 +#define BMI_NUM_OF_DMAS_MASK 0x00000F00 +#define BMI_NUM_OF_EXTRA_DMAS_MASK 0x0000000F +#define BMI_FIFO_SIZE_MASK 0x000003FF +#define BMI_EXTRA_FIFO_SIZE_MASK 0x03FF0000 +#define BMI_CFG2_DMAS_MASK 0x0000003F +#define BMI_TOTAL_FIFO_SIZE_MASK 0x07FF0000 +#define BMI_TOTAL_NUM_OF_TASKS_MASK 0x007F0000 + +/* shifts */ +#define BMI_CFG2_TASKS_SHIFT 16 +#define BMI_CFG2_DMAS_SHIFT 0 +#define BMI_CFG1_FIFO_SIZE_SHIFT 16 +#define BMI_FIFO_SIZE_SHIFT 0 +#define BMI_EXTRA_FIFO_SIZE_SHIFT 16 +#define BMI_NUM_OF_TASKS_SHIFT 24 +#define BMI_EXTRA_NUM_OF_TASKS_SHIFT 16 +#define BMI_NUM_OF_DMAS_SHIFT 8 +#define BMI_EXTRA_NUM_OF_DMAS_SHIFT 0 + +/* others */ +#define BMI_FIFO_ALIGN 0x100 +#define FMAN_BMI_FIFO_UNITS 0x100 + + +/**************************************************************************//** + @Description QMI defines +*//***************************************************************************/ +/* masks */ +#define QMI_CFG_ENQ_EN 0x80000000 +#define QMI_CFG_DEQ_EN 0x40000000 +#define QMI_CFG_EN_COUNTERS 0x10000000 +#define QMI_CFG_SOFT_RESET 0x01000000 +#define QMI_CFG_DEQ_MASK 0x0000003F +#define QMI_CFG_ENQ_MASK 0x00003F00 + +#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000 +#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000 +#define QMI_INTR_EN_SINGLE_ECC 0x80000000 + +/* shifts */ +#define QMI_CFG_ENQ_SHIFT 8 +#define QMI_TAPC_TAP 22 + +#define QMI_GS_HALT_NOT_BUSY 0x00000002 + + +/**************************************************************************//** + @Description IRAM defines +*//***************************************************************************/ +/* masks */ +#define IRAM_IADD_AIE 0x80000000 +#define IRAM_READY 0x80000000 + +uint32_t fman_get_bmi_err_event(struct fman_bmi_regs *bmi_rg); +uint32_t fman_get_qmi_err_event(struct fman_qmi_regs *qmi_rg); +uint32_t fman_get_dma_com_id(struct fman_dma_regs *dma_rg); +uint64_t fman_get_dma_addr(struct fman_dma_regs *dma_rg); +uint32_t fman_get_dma_err_event(struct fman_dma_regs *dma_rg); +uint32_t fman_get_fpm_err_event(struct fman_fpm_regs *fpm_rg); +uint32_t fman_get_muram_err_event(struct fman_fpm_regs *fpm_rg); +uint32_t fman_get_iram_err_event(struct fman_fpm_regs *fpm_rg); +uint32_t fman_get_qmi_event(struct fman_qmi_regs *qmi_rg); +uint32_t fman_get_fpm_error_interrupts(struct fman_fpm_regs *fpm_rg); +uint32_t fman_get_ctrl_intr(struct fman_fpm_regs *fpm_rg, + uint8_t event_reg_id); +uint8_t fman_get_qmi_deq_th(struct fman_qmi_regs *qmi_rg); +uint8_t fman_get_qmi_enq_th(struct fman_qmi_regs *qmi_rg); +uint16_t fman_get_size_of_fifo(struct fman_bmi_regs *bmi_rg, uint8_t port_id); +uint32_t fman_get_total_fifo_size(struct fman_bmi_regs *bmi_rg); +uint16_t fman_get_size_of_extra_fifo(struct fman_bmi_regs *bmi_rg, + uint8_t port_id); +uint8_t fman_get_num_of_tasks(struct fman_bmi_regs *bmi_rg, uint8_t port_id); +uint8_t fman_get_num_extra_tasks(struct fman_bmi_regs *bmi_rg, + uint8_t port_id); +uint8_t fman_get_num_of_dmas(struct fman_bmi_regs *bmi_rg, uint8_t port_id); +uint8_t fman_get_num_extra_dmas(struct fman_bmi_regs *bmi_rg, + uint8_t port_id); +uint32_t fman_get_normal_pending(struct fman_fpm_regs *fpm_rg); +uint32_t fman_get_controller_event(struct fman_fpm_regs *fpm_rg, + uint8_t reg_id); +uint32_t fman_get_error_pending(struct fman_fpm_regs *fpm_rg); +void fman_get_revision(struct fman_fpm_regs *fpm_rg, uint8_t *major, + uint8_t *minor); +uint32_t fman_get_counter(struct fman_rg *fman_rg, + enum fman_counters reg_name); +uint32_t fman_get_dma_status(struct fman_dma_regs *dma_rg); + + +int fman_set_erratum_10gmac_a004_wa(struct fman_fpm_regs *fpm_rg); +void fman_set_ctrl_intr(struct fman_fpm_regs *fpm_rg, uint8_t event_reg_id, + uint32_t enable_events); +void fman_set_num_of_riscs_per_port(struct fman_fpm_regs *fpm_rg, + uint8_t port_id, + uint8_t num_fman_ctrls, + uint32_t or_fman_ctrl); +void fman_set_order_restoration_per_port(struct fman_fpm_regs *fpm_rg, + uint8_t port_id, + bool independent_mode, + bool is_rx_port); +void fman_set_qmi_enq_th(struct fman_qmi_regs *qmi_rg, uint8_t val); +void fman_set_qmi_deq_th(struct fman_qmi_regs *qmi_rg, uint8_t val); +void fman_set_liodn_per_port(struct fman_rg *fman_rg, + uint8_t port_id, + uint16_t liodn_base, + uint16_t liodn_offset); +void fman_set_size_of_fifo(struct fman_bmi_regs *bmi_rg, + uint8_t port_id, + uint32_t size_of_fifo, + uint32_t extra_size_of_fifo); +void fman_set_num_of_tasks(struct fman_bmi_regs *bmi_rg, + uint8_t port_id, + uint8_t num_of_tasks, + uint8_t num_of_extra_tasks); +void fman_set_num_of_open_dmas(struct fman_bmi_regs *bmi_rg, + uint8_t port_id, + uint8_t num_of_open_dmas, + uint8_t num_of_extra_open_dmas, + uint8_t total_num_of_dmas); +void fman_set_ports_bandwidth(struct fman_bmi_regs *bmi_rg, uint8_t *weights); +int fman_set_exception(struct fman_rg *fman_rg, + enum fman_exceptions exception, + bool enable); +void fman_set_dma_emergency(struct fman_dma_regs *dma_rg, bool is_write, + bool enable); +void fman_set_dma_ext_bus_pri(struct fman_dma_regs *dma_rg, uint32_t pri); +void fman_set_congestion_group_pfc_priority(uint32_t *cpg_rg, + uint32_t congestion_group_id, + uint8_t priority_bit_map); + + +void fman_defconfig(struct fman_cfg *cfg, bool is_master); +void fman_regconfig(struct fman_rg *fman_rg, struct fman_cfg *cfg); +int fman_fpm_init(struct fman_fpm_regs *fpm_rg, struct fman_cfg *cfg); +int fman_bmi_init(struct fman_bmi_regs *bmi_rg, struct fman_cfg *cfg); +int fman_qmi_init(struct fman_qmi_regs *qmi_rg, struct fman_cfg *cfg); +int fman_dma_init(struct fman_dma_regs *dma_rg, struct fman_cfg *cfg); +void fman_free_resources(struct fman_rg *fman_rg); +int fman_enable(struct fman_rg *fman_rg, struct fman_cfg *cfg); +void fman_reset(struct fman_fpm_regs *fpm_rg); +void fman_resume(struct fman_fpm_regs *fpm_rg); + + +void fman_enable_time_stamp(struct fman_fpm_regs *fpm_rg, + uint8_t count1ubit, + uint16_t fm_clk_freq); +void fman_enable_rams_ecc(struct fman_fpm_regs *fpm_rg); +void fman_qmi_disable_dispatch_limit(struct fman_fpm_regs *fpm_rg); +void fman_disable_rams_ecc(struct fman_fpm_regs *fpm_rg); +void fman_resume_stalled_port(struct fman_fpm_regs *fpm_rg, uint8_t port_id); +int fman_reset_mac(struct fman_fpm_regs *fpm_rg, uint8_t macId, bool is_10g); +bool fman_is_port_stalled(struct fman_fpm_regs *fpm_rg, uint8_t port_id); +bool fman_rams_ecc_is_external_ctl(struct fman_fpm_regs *fpm_rg); +bool fman_is_qmi_halt_not_busy_state(struct fman_qmi_regs *qmi_rg); +int fman_modify_counter(struct fman_rg *fman_rg, + enum fman_counters reg_name, + uint32_t val); +void fman_force_intr(struct fman_rg *fman_rg, + enum fman_exceptions exception); +void fman_set_vsp_window(struct fman_bmi_regs *bmi_rg, + uint8_t port_id, + uint8_t base_storage_profile, + uint8_t log2_num_of_profiles); + +/**************************************************************************//** + @Description default values +*//***************************************************************************/ +#define DEFAULT_CATASTROPHIC_ERR E_FMAN_CATAST_ERR_STALL_PORT +#define DEFAULT_DMA_ERR E_FMAN_DMA_ERR_CATASTROPHIC +#define DEFAULT_HALT_ON_EXTERNAL_ACTIVATION FALSE /* do not change! if changed, must be disabled for rev1 ! */ +#define DEFAULT_HALT_ON_UNRECOVERABLE_ECC_ERROR FALSE /* do not change! if changed, must be disabled for rev1 ! */ +#define DEFAULT_EXTERNAL_ECC_RAMS_ENABLE FALSE +#define DEFAULT_AID_OVERRIDE FALSE +#define DEFAULT_AID_MODE E_FMAN_DMA_AID_OUT_TNUM +#define DEFAULT_DMA_COMM_Q_LOW 0x2A +#define DEFAULT_DMA_COMM_Q_HIGH 0x3F +#define DEFAULT_CACHE_OVERRIDE E_FMAN_DMA_NO_CACHE_OR +#define DEFAULT_DMA_CAM_NUM_OF_ENTRIES 64 +#define DEFAULT_DMA_DBG_CNT_MODE E_FMAN_DMA_DBG_NO_CNT +#define DEFAULT_DMA_EN_EMERGENCY FALSE +#define DEFAULT_DMA_SOS_EMERGENCY 0 +#define DEFAULT_DMA_WATCHDOG 0 /* disabled */ +#define DEFAULT_DMA_EN_EMERGENCY_SMOOTHER FALSE +#define DEFAULT_DMA_EMERGENCY_SWITCH_COUNTER 0 +#define DEFAULT_DISP_LIMIT 0 +#define DEFAULT_PRS_DISP_TH 16 +#define DEFAULT_PLCR_DISP_TH 16 +#define DEFAULT_KG_DISP_TH 16 +#define DEFAULT_BMI_DISP_TH 16 +#define DEFAULT_QMI_ENQ_DISP_TH 16 +#define DEFAULT_QMI_DEQ_DISP_TH 16 +#define DEFAULT_FM_CTL1_DISP_TH 16 +#define DEFAULT_FM_CTL2_DISP_TH 16 +#define DEFAULT_TNUM_AGING_PERIOD 4 + #endif /* __FSL_FMAN_H */ diff --git a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_dtsec.h b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_dtsec.h index 628ef3a..940087e 100644 --- a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_dtsec.h +++ b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_dtsec.h @@ -41,8 +41,8 @@ * * To prepare dTSEC block for transfer use the following call sequence: * - * - fman_dtsec_defconfig() - This step is optional and yet recommended. Its use is - * to obtain the default dTSEC configuration parameters. + * - fman_dtsec_defconfig() - This step is optional and yet recommended. Its + * use is to obtain the default dTSEC configuration parameters. * * - Change dtsec configuration in &dtsec_cfg. This structure will be used * to customize the dTSEC behavior. @@ -63,12 +63,12 @@ /** * DOC: dTSEC Graceful stop * - * To temporary stop dTSEC activity use fman_dtsec_stop_tx() and fman_dtsec_stop_rx(). - * Note that these functions request dTSEC graceful stop but return before this - * stop is complete. To query for graceful stop completion use - * fman_dtsec_get_event() and check DTSEC_IEVENT_GTSC and DTSEC_IEVENT_GRSC bits. - * Alternatively the dTSEC interrupt mask can be set to enable graceful stop - * interrupts. + * To temporary stop dTSEC activity use fman_dtsec_stop_tx() and + * fman_dtsec_stop_rx(). Note that these functions request dTSEC graceful stop + * but return before this stop is complete. To query for graceful stop + * completion use fman_dtsec_get_event() and check DTSEC_IEVENT_GTSC and + * DTSEC_IEVENT_GRSC bits. Alternatively the dTSEC interrupt mask can be set to + * enable graceful stop interrupts. * * To resume operation after graceful stop use fman_dtsec_start_tx() and * fman_dtsec_start_rx(). @@ -96,8 +96,8 @@ * To poll for event status use the fman_dtsec_get_event() function. * To configure the interrupt mask use fman_dtsec_enable_interrupt() and * fman_dtsec_disable_interrupt() functions. - * After servicing a dTSEC interrupt use fman_dtsec_ack_event to reset the serviced - * event bit. + * After servicing a dTSEC interrupt use fman_dtsec_ack_event to reset the + * serviced event bit. * * The following events may be signaled by dTSEC hardware: * @@ -185,7 +185,7 @@ #define DTSEC_IMASK_TDPEEN 0x00000002 #define DTSEC_IMASK_RDPEEN 0x00000001 -#define DTSEC_EVENTS_MASK \ +#define DTSEC_EVENTS_MASK \ ((uint32_t)(DTSEC_IMASK_BREN | \ DTSEC_IMASK_RXCEN | \ DTSEC_IMASK_BTEN | \ @@ -614,6 +614,17 @@ enum dtsec_stat_counters { E_DTSEC_STAT_TDRP }; +enum dtsec_stat_level { + /* No statistics */ + E_MAC_STAT_NONE = 0, + /* Only RMON MIB group 1 (ether stats). Optimized for performance */ + E_MAC_STAT_MIB_GRP1, + /* Only error counters are available. Optimized for performance */ + E_MAC_STAT_PARTIAL, + /* All counters available. Not optimized for performance */ + E_MAC_STAT_FULL +}; + /** * struct dtsec_cfg - dTSEC configuration @@ -679,8 +690,8 @@ enum dtsec_stat_counters { * precedes the layer 2 header. * * This structure contains basic dTSEC configuration and must be passed to - * fman_dtsec_init() function. A default set of configuration values can be obtained - * by calling fman_dtsec_defconfig(). + * fman_dtsec_init() function. A default set of configuration values can be + * obtained by calling fman_dtsec_defconfig(). */ struct dtsec_cfg { bool halfdup_on; @@ -795,8 +806,9 @@ uint32_t fman_dtsec_get_revision(struct dtsec_regs *regs); * @macaddr: MAC address array * * This function sets MAC station address. To enable unicast reception call - * this after fman_dtsec_init(). While promiscuous mode is disabled dTSEC will match - * the destination address of received unicast frames against this address. + * this after fman_dtsec_init(). While promiscuous mode is disabled dTSEC will + * match the destination address of received unicast frames against this + * address. */ void fman_dtsec_set_mac_address(struct dtsec_regs *regs, uint8_t *macaddr); @@ -815,8 +827,8 @@ void fman_dtsec_get_mac_address(struct dtsec_regs *regs, uint8_t *macaddr); * Use this function to enable/disable dTSEC L2 address filtering. If the * address filtering is disabled all unicast packets are accepted. * To set dTSEC in promiscuous mode call both fman_dtsec_set_uc_promisc() and - * fman_dtsec_set_mc_promisc() to disable filtering for both unicast and multicast - * addresses. + * fman_dtsec_set_mc_promisc() to disable filtering for both unicast and + * multicast addresses. */ void fman_dtsec_set_uc_promisc(struct dtsec_regs *regs, bool enable); @@ -828,8 +840,8 @@ void fman_dtsec_set_uc_promisc(struct dtsec_regs *regs, bool enable); * @full_dx: True for full-duplex, false for half-duplex. * * This function configures the MAC to function and the desired rates. Use it - * to configure dTSEC after fman_dtsec_init() and whenever the link speed changes - * (for instance following PHY auto-negociation). + * to configure dTSEC after fman_dtsec_init() and whenever the link speed + * changes (for instance following PHY auto-negociation). * * Returns: 0 if successful, an error code otherwise. */ @@ -983,6 +995,18 @@ void fman_dtsec_set_ts(struct dtsec_regs *regs, bool en); void fman_dtsec_set_bucket(struct dtsec_regs *regs, int bucket, bool enable); /** + * dtsec_set_hash_table() - insert a crc code into thr filter table + * @regs: Pointer to dTSEC register block + * @crc: crc to insert + * @mcast: true is this is a multicast address + * @ghtx: true if we are in ghtx mode + * + * This function inserts a crc code into the filter table. + */ +void fman_dtsec_set_hash_table(struct dtsec_regs *regs, uint32_t crc, + bool mcast, bool ghtx); + +/** * fman_dtsec_reset_filter_table() - Resets the address filtering table * @regs: Pointer to dTSEC register block * @mcast: Reset multicast entries @@ -995,7 +1019,8 @@ void fman_dtsec_set_bucket(struct dtsec_regs *regs, int bucket, bool enable); * This does not affect the primary nor the 15 additional addresses configured * using dtsec_set_address() or dtsec_set_match_address(). */ -void fman_dtsec_reset_filter_table(struct dtsec_regs *regs, bool mcast, bool ucast); +void fman_dtsec_reset_filter_table(struct dtsec_regs *regs, bool mcast, + bool ucast); /** * fman_dtsec_set_mc_promisc() - Set multicast promiscous mode @@ -1020,7 +1045,8 @@ void fman_dtsec_set_mc_promisc(struct dtsec_regs *regs, bool enable); * * Returns: error if invalid @level value given. */ -int fman_dtsec_set_stat_level(struct dtsec_regs *regs, enum mac_stat_level level); +int fman_dtsec_set_stat_level(struct dtsec_regs *regs, + enum dtsec_stat_level level); /** * fman_dtsec_reset_stat() - Completely resets all dTSEC HW counters diff --git a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_memac.h b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_memac.h index 314463c..61e37b0 100644 --- a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_memac.h +++ b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_memac.h @@ -361,21 +361,25 @@ uint64_t fman_memac_get_counter(struct memac_regs *regs, enum memac_counters reg_name); void fman_memac_set_tx_pause_frames(struct memac_regs *regs, - uint8_t priority, - uint16_t pauseTime, - uint16_t threshTime); + uint8_t priority, uint16_t pauseTime, uint16_t threshTime); uint16_t fman_memac_get_max_frame_len(struct memac_regs *regs); -void fman_memac_set_exception(struct memac_regs *regs, uint32_t val, bool enable); +void fman_memac_set_exception(struct memac_regs *regs, uint32_t val, + bool enable); void fman_memac_reset_stat(struct memac_regs *regs); void fman_memac_reset(struct memac_regs *regs); +void fman_memac_reset_filter_table(struct memac_regs *regs); + +void fman_memac_set_hash_table_entry(struct memac_regs *regs, uint32_t crc); + void fman_memac_set_hash_table(struct memac_regs *regs, uint32_t val); -void fman_memac_set_rx_ignore_pause_frames(struct memac_regs *regs,bool enable); +void fman_memac_set_rx_ignore_pause_frames(struct memac_regs *regs, + bool enable); uint32_t fman_memac_get_event(struct memac_regs *regs, uint32_t ev_mask); @@ -384,8 +388,8 @@ void fman_memac_ack_event(struct memac_regs *regs, uint32_t ev_mask); uint32_t fman_memac_get_interrupt_mask(struct memac_regs *regs); void fman_memac_adjust_link(struct memac_regs *regs, - enum enet_interface iface_mode, - enum enet_speed speed, bool full_dx); + enum enet_interface iface_mode, + enum enet_speed speed, bool full_dx); diff --git a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_memac_mii_acc.h b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_memac_mii_acc.h new file mode 100755 index 0000000..ff9aaa4 --- /dev/null +++ b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_memac_mii_acc.h @@ -0,0 +1,78 @@ +/* + * Copyright 2008-2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_FMAN_MEMAC_MII_ACC_H +#define __FSL_FMAN_MEMAC_MII_ACC_H + +#include "common/general.h" +#include "fsl_enet.h" +/* MII Management Registers */ +#define MDIO_CFG_CLK_DIV_MASK 0x0000ff80 +#define MDIO_CFG_CLK_DIV_SHIFT 7 +#define MDIO_CFG_HOLD_MASK 0x0000001c +#define MDIO_CFG_ENC45 0x00000040 +#define MDIO_CFG_READ_ERR 0x00000002 +#define MDIO_CFG_BSY 0x00000001 + +#define MDIO_CTL_PHY_ADDR_SHIFT 5 +#define MDIO_CTL_READ 0x00008000 + +#define MDIO_DATA_BSY 0x80000000 + +/*MEMAC Internal PHY Registers - SGMII */ +#define PHY_SGMII_CR_PHY_RESET 0x8000 +#define PHY_SGMII_CR_RESET_AN 0x0200 +#define PHY_SGMII_CR_DEF_VAL 0x1140 +#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001 +#define PHY_SGMII_DEV_ABILITY_1000X 0x01A0 +#define PHY_SGMII_IF_MODE_AN 0x0002 +#define PHY_SGMII_IF_MODE_SGMII 0x0001 +#define PHY_SGMII_IF_MODE_1000X 0x0000 + +/*----------------------------------------------------*/ +/* MII Configuration Control Memory Map Registers */ +/*----------------------------------------------------*/ +struct memac_mii_access_mem_map { + uint32_t mdio_cfg; /* 0x030 */ + uint32_t mdio_ctrl; /* 0x034 */ + uint32_t mdio_data; /* 0x038 */ + uint32_t mdio_addr; /* 0x03c */ +}; + +int fman_memac_mii_read_phy_reg(struct memac_mii_access_mem_map *mii_regs, + uint8_t phy_addr, uint8_t reg, uint16_t *data, + enum enet_speed enet_speed); +int fman_memac_mii_write_phy_reg(struct memac_mii_access_mem_map *mii_regs, + uint8_t phy_addr, uint8_t reg, uint16_t data, + enum enet_speed enet_speed); + +#endif /* __MAC_API_MEMAC_MII_ACC_H */ diff --git a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_port.h b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_port.h new file mode 100755 index 0000000..8a10164 --- /dev/null +++ b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_port.h @@ -0,0 +1,594 @@ +/* + * Copyright 2008-2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_FMAN_PORT_H +#define __FSL_FMAN_PORT_H + +#include "fsl_fman_sp.h" + +/** @Collection Registers bit fields */ + +/** @Description BMI defines */ +#define BMI_EBD_EN 0x80000000 + +#define BMI_PORT_CFG_EN 0x80000000 +#define BMI_PORT_CFG_FDOVR 0x02000000 +#define BMI_PORT_CFG_IM 0x01000000 + +#define BMI_PORT_STATUS_BSY 0x80000000 + +#define BMI_DMA_ATTR_SWP_SHIFT FMAN_SP_DMA_ATTR_SWP_SHIFT +#define BMI_DMA_ATTR_IC_STASH_ON 0x10000000 +#define BMI_DMA_ATTR_HDR_STASH_ON 0x04000000 +#define BMI_DMA_ATTR_SG_STASH_ON 0x01000000 +#define BMI_DMA_ATTR_WRITE_OPTIMIZE FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE + +#define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16 +#define BMI_RX_FIFO_THRESHOLD_ETHE 0x80000000 + +#define BMI_TX_FRAME_END_CS_IGNORE_SHIFT 24 +#define BMI_RX_FRAME_END_CS_IGNORE_SHIFT 24 +#define BMI_RX_FRAME_END_CUT_SHIFT 16 + +#define BMI_IC_TO_EXT_SHIFT FMAN_SP_IC_TO_EXT_SHIFT +#define BMI_IC_FROM_INT_SHIFT FMAN_SP_IC_FROM_INT_SHIFT + +#define BMI_INT_BUF_MARG_SHIFT 28 +#define BMI_EXT_BUF_MARG_START_SHIFT FMAN_SP_EXT_BUF_MARG_START_SHIFT + +#define BMI_CMD_MR_LEAC 0x00200000 +#define BMI_CMD_MR_SLEAC 0x00100000 +#define BMI_CMD_MR_MA 0x00080000 +#define BMI_CMD_MR_DEAS 0x00040000 +#define BMI_CMD_RX_MR_DEF (BMI_CMD_MR_LEAC | \ + BMI_CMD_MR_SLEAC | \ + BMI_CMD_MR_MA | \ + BMI_CMD_MR_DEAS) +#define BMI_CMD_TX_MR_DEF 0 +#define BMI_CMD_OP_MR_DEF (BMI_CMD_MR_DEAS | \ + BMI_CMD_MR_MA) + +#define BMI_CMD_ATTR_ORDER 0x80000000 +#define BMI_CMD_ATTR_SYNC 0x02000000 +#define BMI_CMD_ATTR_COLOR_SHIFT 26 + +#define BMI_FIFO_PIPELINE_DEPTH_SHIFT 12 +#define BMI_NEXT_ENG_FD_BITS_SHIFT 24 +#define BMI_FRAME_END_CS_IGNORE_SHIFT 24 + +#define BMI_COUNTERS_EN 0x80000000 + +#define BMI_EXT_BUF_POOL_VALID FMAN_SP_EXT_BUF_POOL_VALID +#define BMI_EXT_BUF_POOL_EN_COUNTER FMAN_SP_EXT_BUF_POOL_EN_COUNTER +#define BMI_EXT_BUF_POOL_BACKUP FMAN_SP_EXT_BUF_POOL_BACKUP +#define BMI_EXT_BUF_POOL_ID_SHIFT 16 +#define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000 +#define BMI_POOL_DEP_NUM_OF_POOLS_SHIFT 16 + +#define BMI_TX_FIFO_MIN_FILL_SHIFT 16 +#define BMI_TX_FIFO_PIPELINE_DEPTH_SHIFT 12 + +#define MAX_PERFORMANCE_TASK_COMP 64 +#define MAX_PERFORMANCE_RX_QUEUE_COMP 64 +#define MAX_PERFORMANCE_TX_QUEUE_COMP 8 +#define MAX_PERFORMANCE_DMA_COMP 16 +#define MAX_PERFORMANCE_FIFO_COMP 1024 + +#define BMI_PERFORMANCE_TASK_COMP_SHIFT 24 +#define BMI_PERFORMANCE_QUEUE_COMP_SHIFT 16 +#define BMI_PERFORMANCE_DMA_COMP_SHIFT 12 + +#define BMI_RATE_LIMIT_GRAN_TX 16000 /* In Kbps */ +#define BMI_RATE_LIMIT_GRAN_OP 10000 /* In frames */ +#define BMI_RATE_LIMIT_MAX_RATE_IN_GRAN_UNITS 1024 +#define BMI_RATE_LIMIT_MAX_BURST_SIZE 1024 /* In KBytes */ +#define BMI_RATE_LIMIT_MAX_BURST_SHIFT 16 +#define BMI_RATE_LIMIT_HIGH_BURST_SIZE_GRAN 0x80000000 +#define BMI_RATE_LIMIT_SCALE_TSBS_SHIFT 16 +#define BMI_RATE_LIMIT_SCALE_EN 0x80000000 +#define BMI_SG_DISABLE FMAN_SP_SG_DISABLE + +/** @Description QMI defines */ +#define QMI_PORT_CFG_EN 0x80000000 +#define QMI_PORT_CFG_EN_COUNTERS 0x10000000 + +#define QMI_PORT_STATUS_DEQ_TNUM_BSY 0x80000000 +#define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000 + +#define QMI_DEQ_CFG_PRI 0x80000000 +#define QMI_DEQ_CFG_TYPE1 0x10000000 +#define QMI_DEQ_CFG_TYPE2 0x20000000 +#define QMI_DEQ_CFG_TYPE3 0x30000000 +#define QMI_DEQ_CFG_PREFETCH_PARTIAL 0x01000000 +#define QMI_DEQ_CFG_PREFETCH_FULL 0x03000000 +#define QMI_DEQ_CFG_SP_MASK 0xf +#define QMI_DEQ_CFG_SP_SHIFT 20 + + +/** @Description General port defines */ +#define FMAN_PORT_EXT_POOLS_NUM(fm_rev_maj) \ + (((fm_rev_maj) == 4) ? 4 : 8) +#define FMAN_PORT_MAX_EXT_POOLS_NUM 8 +#define FMAN_PORT_OBS_EXT_POOLS_NUM 2 +#define FMAN_PORT_CG_MAP_NUM 8 +#define FMAN_PORT_PRS_RESULT_WORDS_NUM 8 +#define FMAN_PORT_BMI_FIFO_UNITS 0x100 +#define FMAN_PORT_IC_OFFSET_UNITS 0x10 + + +/** @Collection FM Port Register Map */ + +/** @Description BMI Rx port register map */ +struct fman_port_rx_bmi_regs { + uint32_t fmbm_rcfg; /**< Rx Configuration */ + uint32_t fmbm_rst; /**< Rx Status */ + uint32_t fmbm_rda; /**< Rx DMA attributes*/ + uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/ + uint32_t fmbm_rfed; /**< Rx Frame End Data*/ + uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/ + uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/ + uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/ + uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/ + uint32_t fmbm_rfca; /**< Rx Frame Command Attributes.*/ + uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/ + uint32_t fmbm_rpso; /**< Rx Parse Start Offset*/ + uint32_t fmbm_rpp; /**< Rx Policer Profile */ + uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */ + uint32_t fmbm_reth; /**< Rx Excessive Threshold */ + uint32_t reserved003c[1]; /**< (0x03C 0x03F) */ + uint32_t fmbm_rprai[FMAN_PORT_PRS_RESULT_WORDS_NUM]; + /**< Rx Parse Results Array Init*/ + uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/ + uint32_t fmbm_refqid; /**< Rx Error Frame Queue ID*/ + uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/ + uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/ + uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */ + uint32_t reserved0074[0x2]; /**< (0x074-0x07C) */ + uint32_t fmbm_rcmne; /**< Rx Frame Continuous Mode Next Engine */ + uint32_t reserved0080[0x20];/**< (0x080 0x0FF) */ + uint32_t fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM]; + /**< Buffer Manager pool Information-*/ + uint32_t fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM]; + /**< Allocate Counter-*/ + uint32_t reserved0130[8]; + /**< 0x130/0x140 - 0x15F reserved -*/ + uint32_t fmbm_rcgm[FMAN_PORT_CG_MAP_NUM]; + /**< Congestion Group Map*/ + uint32_t fmbm_mpd; /**< BM Pool Depletion */ + uint32_t reserved0184[0x1F]; /**< (0x184 0x1FF) */ + uint32_t fmbm_rstc; /**< Rx Statistics Counters*/ + uint32_t fmbm_rfrc; /**< Rx Frame Counter*/ + uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/ + uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/ + uint32_t fmbm_rffc; /**< Rx Filter Frames Counter*/ + uint32_t fmbm_rfdc; /**< Rx Frame Discard Counter*/ + uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/ + uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard nntr*/ + uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter*/ + uint32_t reserved0224[0x17]; /**< (0x224 0x27F) */ + uint32_t fmbm_rpc; /**< Rx Performance Counters*/ + uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/ + uint32_t fmbm_rccn; /**< Rx Cycle Counter*/ + uint32_t fmbm_rtuc; /**< Rx Tasks Utilization Counter*/ + uint32_t fmbm_rrquc; /**< Rx Receive Queue Utilization cntr*/ + uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/ + uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/ + uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/ + uint32_t reserved02a0[0x18]; /**< (0x2A0 0x2FF) */ + uint32_t fmbm_rdbg; /**< Rx Debug-*/ +}; + +/** @Description BMI Tx port register map */ +struct fman_port_tx_bmi_regs { + uint32_t fmbm_tcfg; /**< Tx Configuration */ + uint32_t fmbm_tst; /**< Tx Status */ + uint32_t fmbm_tda; /**< Tx DMA attributes */ + uint32_t fmbm_tfp; /**< Tx FIFO Parameters */ + uint32_t fmbm_tfed; /**< Tx Frame End Data */ + uint32_t fmbm_ticp; /**< Tx Internal Context Parameters */ + uint32_t fmbm_tfdne; /**< Tx Frame Dequeue Next Engine. */ + uint32_t fmbm_tfca; /**< Tx Frame Command attribute. */ + uint32_t fmbm_tcfqid; /**< Tx Confirmation Frame Queue ID. */ + uint32_t fmbm_tefqid; /**< Tx Frame Error Queue ID */ + uint32_t fmbm_tfene; /**< Tx Frame Enqueue Next Engine */ + uint32_t fmbm_trlmts; /**< Tx Rate Limiter Scale */ + uint32_t fmbm_trlmt; /**< Tx Rate Limiter */ + uint32_t reserved0034[0x0e]; /**< (0x034-0x6c) */ + uint32_t fmbm_tccb; /**< Tx Coarse Classification base */ + uint32_t fmbm_tfne; /**< Tx Frame Next Engine */ + uint32_t fmbm_tpfcm[0x02]; /**< Tx Priority based Flow Control (PFC) Mapping */ + uint32_t fmbm_tcmne; /**< Tx Frame Continuous Mode Next Engine */ + uint32_t reserved0080[0x60]; /**< (0x080-0x200) */ + uint32_t fmbm_tstc; /**< Tx Statistics Counters */ + uint32_t fmbm_tfrc; /**< Tx Frame Counter */ + uint32_t fmbm_tfdc; /**< Tx Frames Discard Counter */ + uint32_t fmbm_tfledc; /**< Tx Frame len error discard cntr */ + uint32_t fmbm_tfufdc; /**< Tx Frame unsprt frmt discard cntr*/ + uint32_t fmbm_tbdc; /**< Tx Buffers Deallocate Counter */ + uint32_t reserved0218[0x1A]; /**< (0x218-0x280) */ + uint32_t fmbm_tpc; /**< Tx Performance Counters*/ + uint32_t fmbm_tpcp; /**< Tx Performance Count Parameters*/ + uint32_t fmbm_tccn; /**< Tx Cycle Counter*/ + uint32_t fmbm_ttuc; /**< Tx Tasks Utilization Counter*/ + uint32_t fmbm_ttcquc; /**< Tx Transmit conf Q util Counter*/ + uint32_t fmbm_tduc; /**< Tx DMA Utilization Counter*/ + uint32_t fmbm_tfuc; /**< Tx FIFO Utilization Counter*/ +}; + +/** @Description BMI O/H port register map */ +struct fman_port_oh_bmi_regs { + uint32_t fmbm_ocfg; /**< O/H Configuration */ + uint32_t fmbm_ost; /**< O/H Status */ + uint32_t fmbm_oda; /**< O/H DMA attributes */ + uint32_t fmbm_oicp; /**< O/H Internal Context Parameters */ + uint32_t fmbm_ofdne; /**< O/H Frame Dequeue Next Engine */ + uint32_t fmbm_ofne; /**< O/H Frame Next Engine */ + uint32_t fmbm_ofca; /**< O/H Frame Command Attributes. */ + uint32_t fmbm_ofpne; /**< O/H Frame Parser Next Engine */ + uint32_t fmbm_opso; /**< O/H Parse Start Offset */ + uint32_t fmbm_opp; /**< O/H Policer Profile */ + uint32_t fmbm_occb; /**< O/H Coarse Classification base */ + uint32_t fmbm_oim; /**< O/H Internal margins*/ + uint32_t fmbm_ofp; /**< O/H Fifo Parameters*/ + uint32_t fmbm_ofed; /**< O/H Frame End Data*/ + uint32_t reserved0030[2]; /**< (0x038 - 0x03F) */ + uint32_t fmbm_oprai[FMAN_PORT_PRS_RESULT_WORDS_NUM]; + /**< O/H Parse Results Array Initialization */ + uint32_t fmbm_ofqid; /**< O/H Frame Queue ID */ + uint32_t fmbm_oefqid; /**< O/H Error Frame Queue ID */ + uint32_t fmbm_ofsdm; /**< O/H Frame Status Discard Mask */ + uint32_t fmbm_ofsem; /**< O/H Frame Status Error Mask */ + uint32_t fmbm_ofene; /**< O/H Frame Enqueue Next Engine */ + uint32_t fmbm_orlmts; /**< O/H Rate Limiter Scale */ + uint32_t fmbm_orlmt; /**< O/H Rate Limiter */ + uint32_t fmbm_ocmne; /**< O/H Continuous Mode Next Engine */ + uint32_t reserved0080[0x20]; /**< 0x080 - 0x0FF Reserved */ + uint32_t fmbm_oebmpi[2]; /**< Buf Mngr Observed Pool Info */ + uint32_t reserved0108[0x16]; /**< 0x108 - 0x15F Reserved */ + uint32_t fmbm_ocgm; /**< Observed Congestion Group Map */ + uint32_t reserved0164[0x7]; /**< 0x164 - 0x17F Reserved */ + uint32_t fmbm_ompd; /**< Observed BMan Pool Depletion */ + uint32_t reserved0184[0x1F]; /**< 0x184 - 0x1FF Reserved */ + uint32_t fmbm_ostc; /**< O/H Statistics Counters */ + uint32_t fmbm_ofrc; /**< O/H Frame Counter */ + uint32_t fmbm_ofdc; /**< O/H Frames Discard Counter */ + uint32_t fmbm_ofledc; /**< O/H Frames Len Err Discard Cntr */ + uint32_t fmbm_ofufdc; /**< O/H Frames Unsprtd Discard Cutr */ + uint32_t fmbm_offc; /**< O/H Filter Frames Counter */ + uint32_t fmbm_ofwdc; /**< Rx Frames WRED Discard Counter */ + uint32_t fmbm_ofldec; /**< O/H Frames List DMA Error Cntr */ + uint32_t fmbm_obdc; /**< O/H Buffers Deallocate Counter */ + uint32_t reserved0218[0x17]; /**< (0x218 - 0x27F) */ + uint32_t fmbm_opc; /**< O/H Performance Counters */ + uint32_t fmbm_opcp; /**< O/H Performance Count Parameters */ + uint32_t fmbm_occn; /**< O/H Cycle Counter */ + uint32_t fmbm_otuc; /**< O/H Tasks Utilization Counter */ + uint32_t fmbm_oduc; /**< O/H DMA Utilization Counter */ + uint32_t fmbm_ofuc; /**< O/H FIFO Utilization Counter */ +}; + +/** @Description BMI port register map */ +union fman_port_bmi_regs { + struct fman_port_rx_bmi_regs rx; + struct fman_port_tx_bmi_regs tx; + struct fman_port_oh_bmi_regs oh; +}; + +/** @Description QMI port register map */ +struct fman_port_qmi_regs { + uint32_t fmqm_pnc; /**< PortID n Configuration Register */ + uint32_t fmqm_pns; /**< PortID n Status Register */ + uint32_t fmqm_pnts; /**< PortID n Task Status Register */ + uint32_t reserved00c[4]; /**< 0xn00C - 0xn01B */ + uint32_t fmqm_pnen; /**< PortID n Enqueue NIA Register */ + uint32_t fmqm_pnetfc; /**< PortID n Enq Total Frame Counter */ + uint32_t reserved024[2]; /**< 0xn024 - 0x02B */ + uint32_t fmqm_pndn; /**< PortID n Dequeue NIA Register */ + uint32_t fmqm_pndc; /**< PortID n Dequeue Config Register */ + uint32_t fmqm_pndtfc; /**< PortID n Dequeue tot Frame cntr */ + uint32_t fmqm_pndfdc; /**< PortID n Dequeue FQID Dflt Cntr */ + uint32_t fmqm_pndcc; /**< PortID n Dequeue Confirm Counter */ +}; + + +enum fman_port_dma_swap { + E_FMAN_PORT_DMA_NO_SWAP, /**< No swap, transfer data as is */ + E_FMAN_PORT_DMA_SWAP_LE, + /**< The transferred data should be swapped in PPC Little Endian mode */ + E_FMAN_PORT_DMA_SWAP_BE + /**< The transferred data should be swapped in Big Endian mode */ +}; + +/* Default port color */ +enum fman_port_color { + E_FMAN_PORT_COLOR_GREEN, /**< Default port color is green */ + E_FMAN_PORT_COLOR_YELLOW, /**< Default port color is yellow */ + E_FMAN_PORT_COLOR_RED, /**< Default port color is red */ + E_FMAN_PORT_COLOR_OVERRIDE /**< Ignore color */ +}; + +/* QMI dequeue from the SP channel - types */ +enum fman_port_deq_type { + E_FMAN_PORT_DEQ_BY_PRI, + /**< Priority precedence and Intra-Class scheduling */ + E_FMAN_PORT_DEQ_ACTIVE_FQ, + /**< Active FQ precedence and Intra-Class scheduling */ + E_FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS + /**< Active FQ precedence and override Intra-Class scheduling */ +}; + +/* QMI dequeue prefetch modes */ +enum fman_port_deq_prefetch { + E_FMAN_PORT_DEQ_NO_PREFETCH, /**< No prefetch mode */ + E_FMAN_PORT_DEQ_PART_PREFETCH, /**< Partial prefetch mode */ + E_FMAN_PORT_DEQ_FULL_PREFETCH /**< Full prefetch mode */ +}; + +/* Parameters for defining performance counters behavior */ +struct fman_port_perf_cnt_params { + uint8_t task_val; /**< Task compare value */ + uint8_t queue_val; + /**< Rx or Tx conf queue compare value (unused for O/H ports) */ + uint8_t dma_val; /**< Dma compare value */ + uint32_t fifo_val; /**< Fifo compare value (in bytes) */ +}; + +/** @Description FM Port configuration structure, used at init */ +struct fman_port_cfg { + struct fman_port_perf_cnt_params perf_cnt_params; + /* BMI parameters */ + enum fman_port_dma_swap dma_swap_data; + bool dma_ic_stash_on; + bool dma_header_stash_on; + bool dma_sg_stash_on; + bool dma_write_optimize; + uint16_t ic_ext_offset; + uint8_t ic_int_offset; + uint16_t ic_size; + enum fman_port_color color; + bool sync_req; + bool discard_override; + uint8_t checksum_bytes_ignore; + uint8_t rx_cut_end_bytes; + uint32_t rx_pri_elevation; + uint32_t rx_fifo_thr; + uint8_t rx_fd_bits; + uint8_t int_buf_start_margin; + uint16_t ext_buf_start_margin; + uint16_t ext_buf_end_margin; + uint32_t tx_fifo_min_level; + uint32_t tx_fifo_low_comf_level; + uint8_t tx_fifo_deq_pipeline_depth; + bool stats_counters_enable; + bool perf_counters_enable; + /* QMI parameters */ + bool deq_high_pri; + enum fman_port_deq_type deq_type; + enum fman_port_deq_prefetch deq_prefetch_opt; + uint16_t deq_byte_cnt; + bool queue_counters_enable; + bool no_scatter_gather; + int errata_A006675; + int errata_A006320; + int excessive_threshold_register; + int fmbm_rebm_has_sgd; + int fmbm_tfne_has_features; + int qmi_deq_options_support; +}; + +enum fman_port_type { + E_FMAN_PORT_TYPE_OP = 0, + /**< Offline parsing port, shares id-s with + * host command, so must have exclusive id-s */ + E_FMAN_PORT_TYPE_RX, /**< 1G Rx port */ + E_FMAN_PORT_TYPE_RX_10G, /**< 10G Rx port */ + E_FMAN_PORT_TYPE_TX, /**< 1G Tx port */ + E_FMAN_PORT_TYPE_TX_10G, /**< 10G Tx port */ + E_FMAN_PORT_TYPE_DUMMY, + E_FMAN_PORT_TYPE_HC = E_FMAN_PORT_TYPE_DUMMY + /**< Host command port, shares id-s with + * offline parsing ports, so must have exclusive id-s */ +}; + +struct fman_port_params { + uint32_t discard_mask; + uint32_t err_mask; + uint32_t dflt_fqid; + uint32_t err_fqid; + uint8_t deq_sp; + bool dont_release_buf; +}; + +/* Port context - used by most API functions */ +struct fman_port { + enum fman_port_type type; + uint8_t fm_rev_maj; + uint8_t fm_rev_min; + union fman_port_bmi_regs *bmi_regs; + struct fman_port_qmi_regs *qmi_regs; + bool im_en; + uint8_t ext_pools_num; +}; + +/** @Description External buffer pools configuration */ +struct fman_port_bpools { + uint8_t count; /**< Num of pools to set up */ + bool counters_enable; /**< Enable allocate counters */ + uint8_t grp_bp_depleted_num; + /**< Number of depleted pools - if reached the BMI indicates + * the MAC to send a pause frame */ + struct { + uint8_t bpid; /**< BM pool ID */ + uint16_t size; + /**< Pool's size - must be in ascending order */ + bool is_backup; + /**< If this is a backup pool */ + bool grp_bp_depleted; + /**< Consider this buffer in multiple pools depletion criteria*/ + bool single_bp_depleted; + /**< Consider this buffer in single pool depletion criteria */ + bool pfc_priorities_en; + } bpool[FMAN_PORT_MAX_EXT_POOLS_NUM]; +}; + +enum fman_port_rate_limiter_scale_down { + E_FMAN_PORT_RATE_DOWN_NONE, + E_FMAN_PORT_RATE_DOWN_BY_2, + E_FMAN_PORT_RATE_DOWN_BY_4, + E_FMAN_PORT_RATE_DOWN_BY_8 +}; + +/* Rate limiter configuration */ +struct fman_port_rate_limiter { + uint8_t count_1micro_bit; + bool high_burst_size_gran; + /**< Defines burst_size granularity for OP ports; when TRUE, + * burst_size below counts in frames, otherwise in 10^3 frames */ + uint16_t burst_size; + /**< Max burst size, in KBytes for Tx port, according to + * high_burst_size_gran definition for OP port */ + uint32_t rate; + /**< In Kbps for Tx port, in frames/sec for OP port */ + enum fman_port_rate_limiter_scale_down rate_factor; +}; + +/* BMI statistics counters */ +enum fman_port_stats_counters { + E_FMAN_PORT_STATS_CNT_FRAME, + /**< Number of processed frames; valid for all ports */ + E_FMAN_PORT_STATS_CNT_DISCARD, + /**< For Rx ports - frames discarded by QMAN, for Tx or O/H ports - + * frames discarded due to DMA error; valid for all ports */ + E_FMAN_PORT_STATS_CNT_DEALLOC_BUF, + /**< Number of buffer deallocate operations; valid for all ports */ + E_FMAN_PORT_STATS_CNT_RX_BAD_FRAME, + /**< Number of bad Rx frames, like CRC error, Rx FIFO overflow etc; + * valid for Rx ports only */ + E_FMAN_PORT_STATS_CNT_RX_LARGE_FRAME, + /**< Number of Rx oversized frames, that is frames exceeding max frame + * size configured for the corresponding ETH controller; + * valid for Rx ports only */ + E_FMAN_PORT_STATS_CNT_RX_OUT_OF_BUF, + /**< Frames discarded due to lack of external buffers; valid for + * Rx ports only */ + E_FMAN_PORT_STATS_CNT_LEN_ERR, + /**< Frames discarded due to frame length error; valid for Tx and + * O/H ports only */ + E_FMAN_PORT_STATS_CNT_UNSUPPORTED_FORMAT, + /**< Frames discarded due to unsupported FD format; valid for Tx + * and O/H ports only */ + E_FMAN_PORT_STATS_CNT_FILTERED_FRAME, + /**< Number of frames filtered out by PCD module; valid for + * Rx and OP ports only */ + E_FMAN_PORT_STATS_CNT_DMA_ERR, + /**< Frames rejected by QMAN that were not able to release their + * buffers due to DMA error; valid for Rx and O/H ports only */ + E_FMAN_PORT_STATS_CNT_WRED_DISCARD + /**< Frames going through O/H port that were not able to to enter the + * return queue due to WRED algorithm; valid for O/H ports only */ +}; + +/* BMI performance counters */ +enum fman_port_perf_counters { + E_FMAN_PORT_PERF_CNT_CYCLE, /**< Cycle counter */ + E_FMAN_PORT_PERF_CNT_TASK_UTIL, /**< Tasks utilization counter */ + E_FMAN_PORT_PERF_CNT_QUEUE_UTIL, + /**< For Rx ports - Rx queue utilization, for Tx ports - Tx conf queue + * utilization; not valid for O/H ports */ + E_FMAN_PORT_PERF_CNT_DMA_UTIL, /**< DMA utilization counter */ + E_FMAN_PORT_PERF_CNT_FIFO_UTIL, /**< FIFO utilization counter */ + E_FMAN_PORT_PERF_CNT_RX_PAUSE + /**< Number of cycles in which Rx pause activation control is on; + * valid for Rx ports only */ +}; + +/* QMI counters */ +enum fman_port_qmi_counters { + E_FMAN_PORT_ENQ_TOTAL, /**< EnQ tot frame cntr */ + E_FMAN_PORT_DEQ_TOTAL, /**< DeQ tot frame cntr; invalid for Rx ports */ + E_FMAN_PORT_DEQ_FROM_DFLT, + /**< Dequeue from default FQID counter not valid for Rx ports */ + E_FMAN_PORT_DEQ_CONFIRM /**< DeQ confirm cntr invalid for Rx ports */ +}; + + +/** @Collection FM Port API */ +void fman_port_defconfig(struct fman_port_cfg *cfg, enum fman_port_type type); +int fman_port_init(struct fman_port *port, + struct fman_port_cfg *cfg, + struct fman_port_params *params); +int fman_port_enable(struct fman_port *port); +int fman_port_disable(const struct fman_port *port); +int fman_port_set_bpools(const struct fman_port *port, + const struct fman_port_bpools *bp); +int fman_port_set_rate_limiter(struct fman_port *port, + struct fman_port_rate_limiter *rate_limiter); +int fman_port_delete_rate_limiter(struct fman_port *port); +int fman_port_set_err_mask(struct fman_port *port, uint32_t err_mask); +int fman_port_set_discard_mask(struct fman_port *port, uint32_t discard_mask); +int fman_port_modify_rx_fd_bits(struct fman_port *port, + uint8_t rx_fd_bits, + bool add); +int fman_port_set_perf_cnt_params(struct fman_port *port, + struct fman_port_perf_cnt_params *params); +int fman_port_set_stats_cnt_mode(struct fman_port *port, bool enable); +int fman_port_set_perf_cnt_mode(struct fman_port *port, bool enable); +int fman_port_set_queue_cnt_mode(struct fman_port *port, bool enable); +int fman_port_set_bpool_cnt_mode(struct fman_port *port, + uint8_t bpid, + bool enable); +uint32_t fman_port_get_stats_counter(struct fman_port *port, + enum fman_port_stats_counters counter); +void fman_port_set_stats_counter(struct fman_port *port, + enum fman_port_stats_counters counter, + uint32_t value); +uint32_t fman_port_get_perf_counter(struct fman_port *port, + enum fman_port_perf_counters counter); +void fman_port_set_perf_counter(struct fman_port *port, + enum fman_port_perf_counters counter, + uint32_t value); +uint32_t fman_port_get_qmi_counter(struct fman_port *port, + enum fman_port_qmi_counters counter); +void fman_port_set_qmi_counter(struct fman_port *port, + enum fman_port_qmi_counters counter, + uint32_t value); +uint32_t fman_port_get_bpool_counter(struct fman_port *port, uint8_t bpid); +void fman_port_set_bpool_counter(struct fman_port *port, + uint8_t bpid, + uint32_t value); +int fman_port_add_congestion_grps(struct fman_port *port, + uint32_t grps_map[FMAN_PORT_CG_MAP_NUM]); +int fman_port_remove_congestion_grps(struct fman_port *port, + uint32_t grps_map[FMAN_PORT_CG_MAP_NUM]); + + +#endif /* __FSL_FMAN_PORT_H */ diff --git a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_rtc.h b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_rtc.h index aa6fd73..fddf763 100755 --- a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_rtc.h +++ b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_rtc.h @@ -426,4 +426,24 @@ void fman_rtc_set_periodic_pulse(struct rtc_regs *regs, int id, uint32_t val, void fman_rtc_set_ext_trigger(struct rtc_regs *regs, int id, bool enable, bool use_pulse_as_input); +struct fm_rtc_alarm_params { + uint8_t alarm_id; /**< 0 or 1 */ + uint64_t alarm_time; /**< In nanoseconds, the time when the + alarm should go off - must be a + multiple of the RTC period */ + void (*f_alarm_callback)(void* app, uint8_t id); /**< This routine will + be called when RTC reaches alarmTime */ + bool clear_on_expiration; /**< TRUE to turn off the alarm once + expired.*/ +}; + +struct fm_rtc_periodic_pulse_params { + uint8_t periodic_pulse_id; /**< 0 or 1 */ + uint64_t periodic_pulse_period; /**< In Nanoseconds. Must be a multiple + of the RTC period */ + void (*f_periodic_pulse_callback)(void* app, uint8_t id); /**< This + routine will be called every + periodicPulsePeriod. */ +}; + #endif /* __FSL_FMAN_RTC_H */ diff --git a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_tgec.h b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_tgec.h index e031ccf..a037314 100644 --- a/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_tgec.h +++ b/drivers/net/ethernet/freescale/fman/inc/flib/fsl_fman_tgec.h @@ -38,7 +38,7 @@ /* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */ -#define TX_IPG_LENGTH_MASK 0x000003ff +#define TGEC_TX_IPG_LENGTH_MASK 0x000003ff enum tgec_counters { E_TGEC_COUNTER_R64, @@ -106,14 +106,14 @@ enum tgec_counters { #define TGEC_IMASK_RX_ALIGN_ER 0x00000001 #define TGEC_EVENTS_MASK \ - ((uint32_t)(TGEC_IMASK_MDIO_SCAN_EVENT | \ + ((uint32_t)(TGEC_IMASK_MDIO_SCAN_EVENT | \ TGEC_IMASK_MDIO_CMD_CMPL | \ TGEC_IMASK_REM_FAULT | \ TGEC_IMASK_LOC_FAULT | \ TGEC_IMASK_TX_ECC_ER | \ TGEC_IMASK_TX_FIFO_UNFL | \ TGEC_IMASK_TX_FIFO_OVFL | \ - TGEC_IMASK_TX_ER | \ + TGEC_IMASK_TX_ER | \ TGEC_IMASK_RX_FIFO_OVFL | \ TGEC_IMASK_RX_ECC_ER | \ TGEC_IMASK_RX_JAB_FRM | \ @@ -328,8 +328,8 @@ struct tgec_regs { * (increasing bandwidth). * * This structure contains basic TGEC configuration and must be passed to - * fman_tgec_init() function. A default set of configuration values can be obtained - * by calling fman_tgec_defconfig(). + * fman_tgec_init() function. A default set of configuration values can be + * obtained by calling fman_tgec_defconfig(). */ struct tgec_cfg { bool rx_error_discard; @@ -391,7 +391,8 @@ void fman_tgec_reset_stat(struct tgec_regs *regs); * * Returns: Required counter value */ -uint64_t fman_tgec_get_counter(struct tgec_regs *regs, enum tgec_counters reg_name); +uint64_t fman_tgec_get_counter(struct tgec_regs *regs, + enum tgec_counters reg_name); /** * fman_tgec_set_hash_table() - Sets the Hashtable Control Register @@ -453,6 +454,11 @@ void fman_tgec_enable_interrupt(struct tgec_regs *regs, uint32_t ev_mask); void fman_tgec_disable_interrupt(struct tgec_regs *regs, uint32_t ev_mask); +void fman_tgec_reset_filter_table(struct tgec_regs *regs); + +void fman_tgec_set_hash_table_entry(struct tgec_regs *regs, uint32_t crc); + + /** * fman_tgec_get_max_frame_len() - Returns the maximum frame length value * @regs: Pointer to TGEC register block @@ -460,12 +466,14 @@ void fman_tgec_disable_interrupt(struct tgec_regs *regs, uint32_t ev_mask); uint16_t fman_tgec_get_max_frame_len(struct tgec_regs *regs); /** - * fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007() - Initialize the main tgec configuration parameters + * fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007() - Initialize the + * main tgec configuration parameters * @regs: Pointer to TGEC register block * * TODO */ -void fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(struct tgec_regs *regs); +void fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(struct tgec_regs + *regs); #endif /* __FSL_FMAN_TGEC_H */ diff --git a/drivers/net/ethernet/freescale/fman/inc/integrations/T4240/dpaa_integration_ext.h b/drivers/net/ethernet/freescale/fman/inc/integrations/T4240/dpaa_integration_ext.h index b6780b9..6fa8c25 100644 --- a/drivers/net/ethernet/freescale/fman/inc/integrations/T4240/dpaa_integration_ext.h +++ b/drivers/net/ethernet/freescale/fman/inc/integrations/T4240/dpaa_integration_ext.h @@ -231,8 +231,7 @@ typedef enum /* QMI defines */ #define QMI_MAX_NUM_OF_TNUMS 64 -#define QMI_DEF_TNUMS_THRESH 48 - +#define QMI_DEF_TNUMS_THRESH 32 /* FPM defines */ #define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4 @@ -256,7 +255,6 @@ typedef enum #define FM_DEQ_PIPELINE_PARAMS_FOR_OP #define FM_QMI_NO_SINGLE_ECC_EXCEPTION - #define FM_NO_GUARANTEED_RESET_VALUES /* FM errata */ @@ -277,5 +275,7 @@ typedef enum #define RM_MAX_NUM_OF_IB 4 /**< Number of inbound blocks */ #define RM_NUM_OF_IBCU 8 /**< NUmber of classification units in an inbound block */ +/* RMan erratas */ +#define RM_ERRONEOUS_ACK_ERRATA_RMAN_A006756 #endif /* __DPAA_INTEGRATION_EXT_H */ |