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-rw-r--r--drivers/mfd/Kconfig24
-rw-r--r--drivers/mfd/Makefile5
-rw-r--r--drivers/mfd/ab3100-core.c991
-rw-r--r--drivers/mfd/asic3.c312
-rw-r--r--drivers/mfd/da903x.c2
-rw-r--r--drivers/mfd/ezx-pcap.c505
-rw-r--r--drivers/mfd/pcf50633-core.c2
-rw-r--r--drivers/mfd/pcf50633-gpio.c3
-rw-r--r--drivers/mfd/t7l66xb.c2
-rw-r--r--drivers/mfd/tc6387xb.c2
-rw-r--r--drivers/mfd/tc6393xb.c2
-rw-r--r--drivers/mfd/twl4030-core.c2
-rw-r--r--drivers/mfd/twl4030-irq.c2
-rw-r--r--drivers/mfd/wm8350-regmap.c4
-rw-r--r--drivers/mfd/wm8400-core.c2
15 files changed, 1844 insertions, 16 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index ee3927a..491ac0f 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -30,6 +30,7 @@ config MFD_SM501_GPIO
config MFD_ASIC3
bool "Support for Compaq ASIC3"
depends on GENERIC_HARDIRQS && GPIOLIB && ARM
+ select MFD_CORE
---help---
This driver supports the ASIC3 multifunction chip found on many
PDAs (mainly iPAQ and HTC based ones)
@@ -152,7 +153,7 @@ config MFD_WM8400
depends on I2C
help
Support for the Wolfson Microelecronics WM8400 PMIC and audio
- CODEC. This driver adds provides common support for accessing
+ CODEC. This driver provides common support for accessing
the device, additional drivers must be enabled in order to use
the functionality of the device.
@@ -241,6 +242,27 @@ config PCF50633_GPIO
Say yes here if you want to include support GPIO for pins on
the PCF50633 chip.
+config AB3100_CORE
+ tristate "ST-Ericsson AB3100 Mixed Signal Circuit core functions"
+ depends on I2C
+ default y if ARCH_U300
+ help
+ Select this to enable the AB3100 Mixed Signal IC core
+ functionality. This connects to a AB3100 on the I2C bus
+ and expose a number of symbols needed for dependent devices
+ to read and write registers and subscribe to events from
+ this multi-functional IC. This is needed to use other features
+ of the AB3100 such as battery-backed RTC, charging control,
+ LEDs, vibrator, system power and temperature, power management
+ and ALSA sound.
+
+config EZX_PCAP
+ bool "PCAP Support"
+ depends on GENERIC_HARDIRQS && SPI_MASTER
+ help
+ This enables the PCAP ASIC present on EZX Phones. This is
+ needed for MMC, TouchScreen, Sound, USB, etc..
+
endmenu
menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 3afb519..6f8a9a1af 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -26,6 +26,8 @@ obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-irq.o
obj-$(CONFIG_MFD_CORE) += mfd-core.o
+obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o
+
obj-$(CONFIG_MCP) += mcp-core.o
obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o
obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o
@@ -40,4 +42,5 @@ obj-$(CONFIG_PMIC_DA903X) += da903x.o
obj-$(CONFIG_MFD_PCF50633) += pcf50633-core.o
obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o
-obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o \ No newline at end of file
+obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o
+obj-$(CONFIG_AB3100_CORE) += ab3100-core.o
diff --git a/drivers/mfd/ab3100-core.c b/drivers/mfd/ab3100-core.c
new file mode 100644
index 0000000..13e7d7b
--- /dev/null
+++ b/drivers/mfd/ab3100-core.c
@@ -0,0 +1,991 @@
+/*
+ * Copyright (C) 2007-2009 ST-Ericsson
+ * License terms: GNU General Public License (GPL) version 2
+ * Low-level core for exclusive access to the AB3100 IC on the I2C bus
+ * and some basic chip-configuration.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+
+#include <linux/i2c.h>
+#include <linux/mutex.h>
+#include <linux/list.h>
+#include <linux/notifier.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
+#include <linux/mfd/ab3100.h>
+
+/* These are the only registers inside AB3100 used in this main file */
+
+/* Interrupt event registers */
+#define AB3100_EVENTA1 0x21
+#define AB3100_EVENTA2 0x22
+#define AB3100_EVENTA3 0x23
+
+/* AB3100 DAC converter registers */
+#define AB3100_DIS 0x00
+#define AB3100_D0C 0x01
+#define AB3100_D1C 0x02
+#define AB3100_D2C 0x03
+#define AB3100_D3C 0x04
+
+/* Chip ID register */
+#define AB3100_CID 0x20
+
+/* AB3100 interrupt registers */
+#define AB3100_IMRA1 0x24
+#define AB3100_IMRA2 0x25
+#define AB3100_IMRA3 0x26
+#define AB3100_IMRB1 0x2B
+#define AB3100_IMRB2 0x2C
+#define AB3100_IMRB3 0x2D
+
+/* System Power Monitoring and control registers */
+#define AB3100_MCA 0x2E
+#define AB3100_MCB 0x2F
+
+/* SIM power up */
+#define AB3100_SUP 0x50
+
+/*
+ * I2C communication
+ *
+ * The AB3100 is usually assigned address 0x48 (7-bit)
+ * The chip is defined in the platform i2c_board_data section.
+ */
+static unsigned short normal_i2c[] = { 0x48, I2C_CLIENT_END };
+I2C_CLIENT_INSMOD_1(ab3100);
+
+u8 ab3100_get_chip_type(struct ab3100 *ab3100)
+{
+ u8 chip = ABUNKNOWN;
+
+ switch (ab3100->chip_id & 0xf0) {
+ case 0xa0:
+ chip = AB3000;
+ break;
+ case 0xc0:
+ chip = AB3100;
+ break;
+ }
+ return chip;
+}
+EXPORT_SYMBOL(ab3100_get_chip_type);
+
+int ab3100_set_register(struct ab3100 *ab3100, u8 reg, u8 regval)
+{
+ u8 regandval[2] = {reg, regval};
+ int err;
+
+ err = mutex_lock_interruptible(&ab3100->access_mutex);
+ if (err)
+ return err;
+
+ /*
+ * A two-byte write message with the first byte containing the register
+ * number and the second byte containing the value to be written
+ * effectively sets a register in the AB3100.
+ */
+ err = i2c_master_send(ab3100->i2c_client, regandval, 2);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (write register): %d\n",
+ err);
+ } else if (err != 2) {
+ dev_err(ab3100->dev,
+ "write error (write register) "
+ "%d bytes transferred (expected 2)\n",
+ err);
+ err = -EIO;
+ } else {
+ /* All is well */
+ err = 0;
+ }
+ mutex_unlock(&ab3100->access_mutex);
+ return 0;
+}
+EXPORT_SYMBOL(ab3100_set_register);
+
+/*
+ * The test registers exist at an I2C bus address up one
+ * from the ordinary base. They are not supposed to be used
+ * in production code, but sometimes you have to do that
+ * anyway. It's currently only used from this file so declare
+ * it static and do not export.
+ */
+static int ab3100_set_test_register(struct ab3100 *ab3100,
+ u8 reg, u8 regval)
+{
+ u8 regandval[2] = {reg, regval};
+ int err;
+
+ err = mutex_lock_interruptible(&ab3100->access_mutex);
+ if (err)
+ return err;
+
+ err = i2c_master_send(ab3100->testreg_client, regandval, 2);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (write test register): %d\n",
+ err);
+ } else if (err != 2) {
+ dev_err(ab3100->dev,
+ "write error (write test register) "
+ "%d bytes transferred (expected 2)\n",
+ err);
+ err = -EIO;
+ } else {
+ /* All is well */
+ err = 0;
+ }
+ mutex_unlock(&ab3100->access_mutex);
+
+ return err;
+}
+
+int ab3100_get_register(struct ab3100 *ab3100, u8 reg, u8 *regval)
+{
+ int err;
+
+ err = mutex_lock_interruptible(&ab3100->access_mutex);
+ if (err)
+ return err;
+
+ /*
+ * AB3100 require an I2C "stop" command between each message, else
+ * it will not work. The only way of achieveing this with the
+ * message transport layer is to send the read and write messages
+ * separately.
+ */
+ err = i2c_master_send(ab3100->i2c_client, &reg, 1);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (send register address): %d\n",
+ err);
+ goto get_reg_out_unlock;
+ } else if (err != 1) {
+ dev_err(ab3100->dev,
+ "write error (send register address) "
+ "%d bytes transferred (expected 1)\n",
+ err);
+ err = -EIO;
+ goto get_reg_out_unlock;
+ } else {
+ /* All is well */
+ err = 0;
+ }
+
+ err = i2c_master_recv(ab3100->i2c_client, regval, 1);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (read register): %d\n",
+ err);
+ goto get_reg_out_unlock;
+ } else if (err != 1) {
+ dev_err(ab3100->dev,
+ "write error (read register) "
+ "%d bytes transferred (expected 1)\n",
+ err);
+ err = -EIO;
+ goto get_reg_out_unlock;
+ } else {
+ /* All is well */
+ err = 0;
+ }
+
+ get_reg_out_unlock:
+ mutex_unlock(&ab3100->access_mutex);
+ return err;
+}
+EXPORT_SYMBOL(ab3100_get_register);
+
+int ab3100_get_register_page(struct ab3100 *ab3100,
+ u8 first_reg, u8 *regvals, u8 numregs)
+{
+ int err;
+
+ if (ab3100->chip_id == 0xa0 ||
+ ab3100->chip_id == 0xa1)
+ /* These don't support paged reads */
+ return -EIO;
+
+ err = mutex_lock_interruptible(&ab3100->access_mutex);
+ if (err)
+ return err;
+
+ /*
+ * Paged read also require an I2C "stop" command.
+ */
+ err = i2c_master_send(ab3100->i2c_client, &first_reg, 1);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (send first register address): %d\n",
+ err);
+ goto get_reg_page_out_unlock;
+ } else if (err != 1) {
+ dev_err(ab3100->dev,
+ "write error (send first register address) "
+ "%d bytes transferred (expected 1)\n",
+ err);
+ err = -EIO;
+ goto get_reg_page_out_unlock;
+ }
+
+ err = i2c_master_recv(ab3100->i2c_client, regvals, numregs);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (read register page): %d\n",
+ err);
+ goto get_reg_page_out_unlock;
+ } else if (err != numregs) {
+ dev_err(ab3100->dev,
+ "write error (read register page) "
+ "%d bytes transferred (expected %d)\n",
+ err, numregs);
+ err = -EIO;
+ goto get_reg_page_out_unlock;
+ }
+
+ /* All is well */
+ err = 0;
+
+ get_reg_page_out_unlock:
+ mutex_unlock(&ab3100->access_mutex);
+ return err;
+}
+EXPORT_SYMBOL(ab3100_get_register_page);
+
+int ab3100_mask_and_set_register(struct ab3100 *ab3100,
+ u8 reg, u8 andmask, u8 ormask)
+{
+ u8 regandval[2] = {reg, 0};
+ int err;
+
+ err = mutex_lock_interruptible(&ab3100->access_mutex);
+ if (err)
+ return err;
+
+ /* First read out the target register */
+ err = i2c_master_send(ab3100->i2c_client, &reg, 1);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (maskset send address): %d\n",
+ err);
+ goto get_maskset_unlock;
+ } else if (err != 1) {
+ dev_err(ab3100->dev,
+ "write error (maskset send address) "
+ "%d bytes transferred (expected 1)\n",
+ err);
+ err = -EIO;
+ goto get_maskset_unlock;
+ }
+
+ err = i2c_master_recv(ab3100->i2c_client, &regandval[1], 1);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (maskset read register): %d\n",
+ err);
+ goto get_maskset_unlock;
+ } else if (err != 1) {
+ dev_err(ab3100->dev,
+ "write error (maskset read register) "
+ "%d bytes transferred (expected 1)\n",
+ err);
+ err = -EIO;
+ goto get_maskset_unlock;
+ }
+
+ /* Modify the register */
+ regandval[1] &= andmask;
+ regandval[1] |= ormask;
+
+ /* Write the register */
+ err = i2c_master_send(ab3100->i2c_client, regandval, 2);
+ if (err < 0) {
+ dev_err(ab3100->dev,
+ "write error (write register): %d\n",
+ err);
+ goto get_maskset_unlock;
+ } else if (err != 2) {
+ dev_err(ab3100->dev,
+ "write error (write register) "
+ "%d bytes transferred (expected 2)\n",
+ err);
+ err = -EIO;
+ goto get_maskset_unlock;
+ }
+
+ /* All is well */
+ err = 0;
+
+ get_maskset_unlock:
+ mutex_unlock(&ab3100->access_mutex);
+ return err;
+}
+EXPORT_SYMBOL(ab3100_mask_and_set_register);
+
+/*
+ * Register a simple callback for handling any AB3100 events.
+ */
+int ab3100_event_register(struct ab3100 *ab3100,
+ struct notifier_block *nb)
+{
+ return blocking_notifier_chain_register(&ab3100->event_subscribers,
+ nb);
+}
+EXPORT_SYMBOL(ab3100_event_register);
+
+/*
+ * Remove a previously registered callback.
+ */
+int ab3100_event_unregister(struct ab3100 *ab3100,
+ struct notifier_block *nb)
+{
+ return blocking_notifier_chain_unregister(&ab3100->event_subscribers,
+ nb);
+}
+EXPORT_SYMBOL(ab3100_event_unregister);
+
+
+int ab3100_event_registers_startup_state_get(struct ab3100 *ab3100,
+ u32 *fatevent)
+{
+ if (!ab3100->startup_events_read)
+ return -EAGAIN; /* Try again later */
+ *fatevent = ab3100->startup_events;
+ return 0;
+}
+EXPORT_SYMBOL(ab3100_event_registers_startup_state_get);
+
+/* Interrupt handling worker */
+static void ab3100_work(struct work_struct *work)
+{
+ struct ab3100 *ab3100 = container_of(work, struct ab3100, work);
+ u8 event_regs[3];
+ u32 fatevent;
+ int err;
+
+ err = ab3100_get_register_page(ab3100, AB3100_EVENTA1,
+ event_regs, 3);
+ if (err)
+ goto err_event_wq;
+
+ fatevent = (event_regs[0] << 16) |
+ (event_regs[1] << 8) |
+ event_regs[2];
+
+ if (!ab3100->startup_events_read) {
+ ab3100->startup_events = fatevent;
+ ab3100->startup_events_read = true;
+ }
+ /*
+ * The notified parties will have to mask out the events
+ * they're interested in and react to them. They will be
+ * notified on all events, then they use the fatevent value
+ * to determine if they're interested.
+ */
+ blocking_notifier_call_chain(&ab3100->event_subscribers,
+ fatevent, NULL);
+
+ dev_dbg(ab3100->dev,
+ "IRQ Event: 0x%08x\n", fatevent);
+
+ /* By now the IRQ should be acked and deasserted so enable it again */
+ enable_irq(ab3100->i2c_client->irq);
+ return;
+
+ err_event_wq:
+ dev_dbg(ab3100->dev,
+ "error in event workqueue\n");
+ /* Enable the IRQ anyway, what choice do we have? */
+ enable_irq(ab3100->i2c_client->irq);
+ return;
+}
+
+static irqreturn_t ab3100_irq_handler(int irq, void *data)
+{
+ struct ab3100 *ab3100 = data;
+ /*
+ * Disable the IRQ and dispatch a worker to handle the
+ * event. Since the chip resides on I2C this is slow
+ * stuff and we will re-enable the interrupts once th
+ * worker has finished.
+ */
+ disable_irq(ab3100->i2c_client->irq);
+ schedule_work(&ab3100->work);
+ return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_DEBUG_FS
+/*
+ * Some debugfs entries only exposed if we're using debug
+ */
+static int ab3100_registers_print(struct seq_file *s, void *p)
+{
+ struct ab3100 *ab3100 = s->private;
+ u8 value;
+ u8 reg;
+
+ seq_printf(s, "AB3100 registers:\n");
+
+ for (reg = 0; reg < 0xff; reg++) {
+ ab3100_get_register(ab3100, reg, &value);
+ seq_printf(s, "[0x%x]: 0x%x\n", reg, value);
+ }
+ return 0;
+}
+
+static int ab3100_registers_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, ab3100_registers_print, inode->i_private);
+}
+
+static const struct file_operations ab3100_registers_fops = {
+ .open = ab3100_registers_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .owner = THIS_MODULE,
+};
+
+struct ab3100_get_set_reg_priv {
+ struct ab3100 *ab3100;
+ bool mode;
+};
+
+static int ab3100_get_set_reg_open_file(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static int ab3100_get_set_reg(struct file *file,
+ const char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct ab3100_get_set_reg_priv *priv = file->private_data;
+ struct ab3100 *ab3100 = priv->ab3100;
+ char buf[32];
+ int buf_size;
+ int regp;
+ unsigned long user_reg;
+ int err;
+ int i = 0;
+
+ /* Get userspace string and assure termination */
+ buf_size = min(count, (sizeof(buf)-1));
+ if (copy_from_user(buf, user_buf, buf_size))
+ return -EFAULT;
+ buf[buf_size] = 0;
+
+ /*
+ * The idea is here to parse a string which is either
+ * "0xnn" for reading a register, or "0xaa 0xbb" for
+ * writing 0xbb to the register 0xaa. First move past
+ * whitespace and then begin to parse the register.
+ */
+ while ((i < buf_size) && (buf[i] == ' '))
+ i++;
+ regp = i;
+
+ /*
+ * Advance pointer to end of string then terminate
+ * the register string. This is needed to satisfy
+ * the strict_strtoul() function.
+ */
+ while ((i < buf_size) && (buf[i] != ' '))
+ i++;
+ buf[i] = '\0';
+
+ err = strict_strtoul(&buf[regp], 16, &user_reg);
+ if (err)
+ return err;
+ if (user_reg > 0xff)
+ return -EINVAL;
+
+ /* Either we read or we write a register here */
+ if (!priv->mode) {
+ /* Reading */
+ u8 reg = (u8) user_reg;
+ u8 regvalue;
+
+ ab3100_get_register(ab3100, reg, &regvalue);
+
+ dev_info(ab3100->dev,
+ "debug read AB3100 reg[0x%02x]: 0x%02x\n",
+ reg, regvalue);
+ } else {
+ int valp;
+ unsigned long user_value;
+ u8 reg = (u8) user_reg;
+ u8 value;
+ u8 regvalue;
+
+ /*
+ * Writing, we need some value to write to
+ * the register so keep parsing the string
+ * from userspace.
+ */
+ i++;
+ while ((i < buf_size) && (buf[i] == ' '))
+ i++;
+ valp = i;
+ while ((i < buf_size) && (buf[i] != ' '))
+ i++;
+ buf[i] = '\0';
+
+ err = strict_strtoul(&buf[valp], 16, &user_value);
+ if (err)
+ return err;
+ if (user_reg > 0xff)
+ return -EINVAL;
+
+ value = (u8) user_value;
+ ab3100_set_register(ab3100, reg, value);
+ ab3100_get_register(ab3100, reg, &regvalue);
+
+ dev_info(ab3100->dev,
+ "debug write reg[0x%02x] with 0x%02x, "
+ "after readback: 0x%02x\n",
+ reg, value, regvalue);
+ }
+ return buf_size;
+}
+
+static const struct file_operations ab3100_get_set_reg_fops = {
+ .open = ab3100_get_set_reg_open_file,
+ .write = ab3100_get_set_reg,
+};
+
+static struct dentry *ab3100_dir;
+static struct dentry *ab3100_reg_file;
+static struct ab3100_get_set_reg_priv ab3100_get_priv;
+static struct dentry *ab3100_get_reg_file;
+static struct ab3100_get_set_reg_priv ab3100_set_priv;
+static struct dentry *ab3100_set_reg_file;
+
+static void ab3100_setup_debugfs(struct ab3100 *ab3100)
+{
+ int err;
+
+ ab3100_dir = debugfs_create_dir("ab3100", NULL);
+ if (!ab3100_dir)
+ goto exit_no_debugfs;
+
+ ab3100_reg_file = debugfs_create_file("registers",
+ S_IRUGO, ab3100_dir, ab3100,
+ &ab3100_registers_fops);
+ if (!ab3100_reg_file) {
+ err = -ENOMEM;
+ goto exit_destroy_dir;
+ }
+
+ ab3100_get_priv.ab3100 = ab3100;
+ ab3100_get_priv.mode = false;
+ ab3100_get_reg_file = debugfs_create_file("get_reg",
+ S_IWUGO, ab3100_dir, &ab3100_get_priv,
+ &ab3100_get_set_reg_fops);
+ if (!ab3100_get_reg_file) {
+ err = -ENOMEM;
+ goto exit_destroy_reg;
+ }
+
+ ab3100_set_priv.ab3100 = ab3100;
+ ab3100_set_priv.mode = true;
+ ab3100_set_reg_file = debugfs_create_file("set_reg",
+ S_IWUGO, ab3100_dir, &ab3100_set_priv,
+ &ab3100_get_set_reg_fops);
+ if (!ab3100_set_reg_file) {
+ err = -ENOMEM;
+ goto exit_destroy_get_reg;
+ }
+ return;
+
+ exit_destroy_get_reg:
+ debugfs_remove(ab3100_get_reg_file);
+ exit_destroy_reg:
+ debugfs_remove(ab3100_reg_file);
+ exit_destroy_dir:
+ debugfs_remove(ab3100_dir);
+ exit_no_debugfs:
+ return;
+}
+static inline void ab3100_remove_debugfs(void)
+{
+ debugfs_remove(ab3100_set_reg_file);
+ debugfs_remove(ab3100_get_reg_file);
+ debugfs_remove(ab3100_reg_file);
+ debugfs_remove(ab3100_dir);
+}
+#else
+static inline void ab3100_setup_debugfs(struct ab3100 *ab3100)
+{
+}
+static inline void ab3100_remove_debugfs(void)
+{
+}
+#endif
+
+/*
+ * Basic set-up, datastructure creation/destruction and I2C interface.
+ * This sets up a default config in the AB3100 chip so that it
+ * will work as expected.
+ */
+
+struct ab3100_init_setting {
+ u8 abreg;
+ u8 setting;
+};
+
+static const struct ab3100_init_setting __initdata
+ab3100_init_settings[] = {
+ {
+ .abreg = AB3100_MCA,
+ .setting = 0x01
+ }, {
+ .abreg = AB3100_MCB,
+ .setting = 0x30
+ }, {
+ .abreg = AB3100_IMRA1,
+ .setting = 0x00
+ }, {
+ .abreg = AB3100_IMRA2,
+ .setting = 0xFF
+ }, {
+ .abreg = AB3100_IMRA3,
+ .setting = 0x01
+ }, {
+ .abreg = AB3100_IMRB1,
+ .setting = 0xFF
+ }, {
+ .abreg = AB3100_IMRB2,
+ .setting = 0xFF
+ }, {
+ .abreg = AB3100_IMRB3,
+ .setting = 0xFF
+ }, {
+ .abreg = AB3100_SUP,
+ .setting = 0x00
+ }, {
+ .abreg = AB3100_DIS,
+ .setting = 0xF0
+ }, {
+ .abreg = AB3100_D0C,
+ .setting = 0x00
+ }, {
+ .abreg = AB3100_D1C,
+ .setting = 0x00
+ }, {
+ .abreg = AB3100_D2C,
+ .setting = 0x00
+ }, {
+ .abreg = AB3100_D3C,
+ .setting = 0x00
+ },
+};
+
+static int __init ab3100_setup(struct ab3100 *ab3100)
+{
+ int err = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ab3100_init_settings); i++) {
+ err = ab3100_set_register(ab3100,
+ ab3100_init_settings[i].abreg,
+ ab3100_init_settings[i].setting);
+ if (err)
+ goto exit_no_setup;
+ }
+
+ /*
+ * Special trick to make the AB3100 use the 32kHz clock (RTC)
+ * bit 3 in test registe 0x02 is a special, undocumented test
+ * register bit that only exist in AB3100 P1E
+ */
+ if (ab3100->chip_id == 0xc4) {
+ dev_warn(ab3100->dev,
+ "AB3100 P1E variant detected, "
+ "forcing chip to 32KHz\n");
+ err = ab3100_set_test_register(ab3100, 0x02, 0x08);
+ }
+
+ exit_no_setup:
+ return err;
+}
+
+/*
+ * Here we define all the platform devices that appear
+ * as children of the AB3100. These are regular platform
+ * devices with the IORESOURCE_IO .start and .end set
+ * to correspond to the internal AB3100 register range
+ * mapping to the corresponding subdevice.
+ */
+
+#define AB3100_DEVICE(devname, devid) \
+static struct platform_device ab3100_##devname##_device = { \
+ .name = devid, \
+ .id = -1, \
+}
+
+/*
+ * This lists all the subdevices and corresponding register
+ * ranges.
+ */
+AB3100_DEVICE(dac, "ab3100-dac");
+AB3100_DEVICE(leds, "ab3100-leds");
+AB3100_DEVICE(power, "ab3100-power");
+AB3100_DEVICE(regulators, "ab3100-regulators");
+AB3100_DEVICE(sim, "ab3100-sim");
+AB3100_DEVICE(uart, "ab3100-uart");
+AB3100_DEVICE(rtc, "ab3100-rtc");
+AB3100_DEVICE(charger, "ab3100-charger");
+AB3100_DEVICE(boost, "ab3100-boost");
+AB3100_DEVICE(adc, "ab3100-adc");
+AB3100_DEVICE(fuelgauge, "ab3100-fuelgauge");
+AB3100_DEVICE(vibrator, "ab3100-vibrator");
+AB3100_DEVICE(otp, "ab3100-otp");
+AB3100_DEVICE(codec, "ab3100-codec");
+
+static struct platform_device *
+ab3100_platform_devs[] = {
+ &ab3100_dac_device,
+ &ab3100_leds_device,
+ &ab3100_power_device,
+ &ab3100_regulators_device,
+ &ab3100_sim_device,
+ &ab3100_uart_device,
+ &ab3100_rtc_device,
+ &ab3100_charger_device,
+ &ab3100_boost_device,
+ &ab3100_adc_device,
+ &ab3100_fuelgauge_device,
+ &ab3100_vibrator_device,
+ &ab3100_otp_device,
+ &ab3100_codec_device,
+};
+
+struct ab_family_id {
+ u8 id;
+ char *name;
+};
+
+static const struct ab_family_id ids[] __initdata = {
+ /* AB3100 */
+ {
+ .id = 0xc0,
+ .name = "P1A"
+ }, {
+ .id = 0xc1,
+ .name = "P1B"
+ }, {
+ .id = 0xc2,
+ .name = "P1C"
+ }, {
+ .id = 0xc3,
+ .name = "P1D"
+ }, {
+ .id = 0xc4,
+ .name = "P1E"
+ }, {
+ .id = 0xc5,
+ .name = "P1F/R1A"
+ }, {
+ .id = 0xc6,
+ .name = "P1G/R1A"
+ }, {
+ .id = 0xc7,
+ .name = "P2A/R2A"
+ }, {
+ .id = 0xc8,
+ .name = "P2B/R2B"
+ },
+ /* AB3000 variants, not supported */
+ {
+ .id = 0xa0
+ }, {
+ .id = 0xa1
+ }, {
+ .id = 0xa2
+ }, {
+ .id = 0xa3
+ }, {
+ .id = 0xa4
+ }, {
+ .id = 0xa5
+ }, {
+ .id = 0xa6
+ }, {
+ .id = 0xa7
+ },
+ /* Terminator */
+ {
+ .id = 0x00,
+ },
+};
+
+static int __init ab3100_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct ab3100 *ab3100;
+ int err;
+ int i;
+
+ ab3100 = kzalloc(sizeof(struct ab3100), GFP_KERNEL);
+ if (!ab3100) {
+ dev_err(&client->dev, "could not allocate AB3100 device\n");
+ return -ENOMEM;
+ }
+
+ /* Initialize data structure */
+ mutex_init(&ab3100->access_mutex);
+ BLOCKING_INIT_NOTIFIER_HEAD(&ab3100->event_subscribers);
+
+ ab3100->i2c_client = client;
+ ab3100->dev = &ab3100->i2c_client->dev;
+
+ i2c_set_clientdata(client, ab3100);
+
+ /* Read chip ID register */
+ err = ab3100_get_register(ab3100, AB3100_CID,
+ &ab3100->chip_id);
+ if (err) {
+ dev_err(&client->dev,
+ "could not communicate with the AB3100 analog "
+ "baseband chip\n");
+ goto exit_no_detect;
+ }
+
+ for (i = 0; ids[i].id != 0x0; i++) {
+ if (ids[i].id == ab3100->chip_id) {
+ if (ids[i].name != NULL) {
+ snprintf(&ab3100->chip_name[0],
+ sizeof(ab3100->chip_name) - 1,
+ "AB3100 %s",
+ ids[i].name);
+ break;
+ } else {
+ dev_err(&client->dev,
+ "AB3000 is not supported\n");
+ goto exit_no_detect;
+ }
+ }
+ }
+
+ if (ids[i].id == 0x0) {
+ dev_err(&client->dev, "unknown analog baseband chip id: 0x%x\n",
+ ab3100->chip_id);
+ dev_err(&client->dev, "accepting it anyway. Please update "
+ "the driver.\n");
+ goto exit_no_detect;
+ }
+
+ dev_info(&client->dev, "Detected chip: %s\n",
+ &ab3100->chip_name[0]);
+
+ /* Attach a second dummy i2c_client to the test register address */
+ ab3100->testreg_client = i2c_new_dummy(client->adapter,
+ client->addr + 1);
+ if (!ab3100->testreg_client) {
+ err = -ENOMEM;
+ goto exit_no_testreg_client;
+ }
+
+ strlcpy(ab3100->testreg_client->name, id->name,
+ sizeof(ab3100->testreg_client->name));
+
+ err = ab3100_setup(ab3100);
+ if (err)
+ goto exit_no_setup;
+
+ INIT_WORK(&ab3100->work, ab3100_work);
+
+ /* This real unpredictable IRQ is of course sampled for entropy */
+ err = request_irq(client->irq, ab3100_irq_handler,
+ IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
+ "AB3100 IRQ", ab3100);
+ if (err)
+ goto exit_no_irq;
+
+ /* Set parent and a pointer back to the container in device data */
+ for (i = 0; i < ARRAY_SIZE(ab3100_platform_devs); i++) {
+ ab3100_platform_devs[i]->dev.parent =
+ &client->dev;
+ platform_set_drvdata(ab3100_platform_devs[i], ab3100);
+ }
+
+ /* Register the platform devices */
+ platform_add_devices(ab3100_platform_devs,
+ ARRAY_SIZE(ab3100_platform_devs));
+
+ ab3100_setup_debugfs(ab3100);
+
+ return 0;
+
+ exit_no_irq:
+ exit_no_setup:
+ i2c_unregister_device(ab3100->testreg_client);
+ exit_no_testreg_client:
+ exit_no_detect:
+ kfree(ab3100);
+ return err;
+}
+
+static int __exit ab3100_remove(struct i2c_client *client)
+{
+ struct ab3100 *ab3100 = i2c_get_clientdata(client);
+ int i;
+
+ /* Unregister subdevices */
+ for (i = 0; i < ARRAY_SIZE(ab3100_platform_devs); i++)
+ platform_device_unregister(ab3100_platform_devs[i]);
+
+ ab3100_remove_debugfs();
+ i2c_unregister_device(ab3100->testreg_client);
+
+ /*
+ * At this point, all subscribers should have unregistered
+ * their notifiers so deactivate IRQ
+ */
+ free_irq(client->irq, ab3100);
+ kfree(ab3100);
+ return 0;
+}
+
+static const struct i2c_device_id ab3100_id[] = {
+ { "ab3100", ab3100 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, ab3100_id);
+
+static struct i2c_driver ab3100_driver = {
+ .driver = {
+ .name = "ab3100",
+ .owner = THIS_MODULE,
+ },
+ .id_table = ab3100_id,
+ .probe = ab3100_probe,
+ .remove = __exit_p(ab3100_remove),
+};
+
+static int __init ab3100_i2c_init(void)
+{
+ return i2c_add_driver(&ab3100_driver);
+}
+
+static void __exit ab3100_i2c_exit(void)
+{
+ i2c_del_driver(&ab3100_driver);
+}
+
+subsys_initcall(ab3100_i2c_init);
+module_exit(ab3100_i2c_exit);
+
+MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
+MODULE_DESCRIPTION("AB3100 core driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c
index 9e48545..63a2a66 100644
--- a/drivers/mfd/asic3.c
+++ b/drivers/mfd/asic3.c
@@ -17,6 +17,7 @@
*/
#include <linux/kernel.h>
+#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/io.h>
@@ -24,6 +25,51 @@
#include <linux/platform_device.h>
#include <linux/mfd/asic3.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/ds1wm.h>
+#include <linux/mfd/tmio.h>
+
+enum {
+ ASIC3_CLOCK_SPI,
+ ASIC3_CLOCK_OWM,
+ ASIC3_CLOCK_PWM0,
+ ASIC3_CLOCK_PWM1,
+ ASIC3_CLOCK_LED0,
+ ASIC3_CLOCK_LED1,
+ ASIC3_CLOCK_LED2,
+ ASIC3_CLOCK_SD_HOST,
+ ASIC3_CLOCK_SD_BUS,
+ ASIC3_CLOCK_SMBUS,
+ ASIC3_CLOCK_EX0,
+ ASIC3_CLOCK_EX1,
+};
+
+struct asic3_clk {
+ int enabled;
+ unsigned int cdex;
+ unsigned long rate;
+};
+
+#define INIT_CDEX(_name, _rate) \
+ [ASIC3_CLOCK_##_name] = { \
+ .cdex = CLOCK_CDEX_##_name, \
+ .rate = _rate, \
+ }
+
+struct asic3_clk asic3_clk_init[] __initdata = {
+ INIT_CDEX(SPI, 0),
+ INIT_CDEX(OWM, 5000000),
+ INIT_CDEX(PWM0, 0),
+ INIT_CDEX(PWM1, 0),
+ INIT_CDEX(LED0, 0),
+ INIT_CDEX(LED1, 0),
+ INIT_CDEX(LED2, 0),
+ INIT_CDEX(SD_HOST, 24576000),
+ INIT_CDEX(SD_BUS, 12288000),
+ INIT_CDEX(SMBUS, 0),
+ INIT_CDEX(EX0, 32768),
+ INIT_CDEX(EX1, 24576000),
+};
struct asic3 {
void __iomem *mapping;
@@ -34,6 +80,8 @@ struct asic3 {
u16 irq_bothedge[4];
struct gpio_chip gpio;
struct device *dev;
+
+ struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
};
static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
@@ -52,6 +100,21 @@ static inline u32 asic3_read_register(struct asic3 *asic,
(reg >> asic->bus_shift));
}
+void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
+{
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&asic->lock, flags);
+ val = asic3_read_register(asic, reg);
+ if (set)
+ val |= bits;
+ else
+ val &= ~bits;
+ asic3_write_register(asic, reg, val);
+ spin_unlock_irqrestore(&asic->lock, flags);
+}
+
/* IRQs */
#define MAX_ASIC_ISR_LOOPS 20
#define ASIC3_GPIO_BASE_INCR \
@@ -525,6 +588,240 @@ static int asic3_gpio_remove(struct platform_device *pdev)
return gpiochip_remove(&asic->gpio);
}
+static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
+{
+ unsigned long flags;
+ u32 cdex;
+
+ spin_lock_irqsave(&asic->lock, flags);
+ if (clk->enabled++ == 0) {
+ cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
+ cdex |= clk->cdex;
+ asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
+ }
+ spin_unlock_irqrestore(&asic->lock, flags);
+
+ return 0;
+}
+
+static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
+{
+ unsigned long flags;
+ u32 cdex;
+
+ WARN_ON(clk->enabled == 0);
+
+ spin_lock_irqsave(&asic->lock, flags);
+ if (--clk->enabled == 0) {
+ cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
+ cdex &= ~clk->cdex;
+ asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
+ }
+ spin_unlock_irqrestore(&asic->lock, flags);
+}
+
+/* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
+static struct ds1wm_driver_data ds1wm_pdata = {
+ .active_high = 1,
+};
+
+static struct resource ds1wm_resources[] = {
+ {
+ .start = ASIC3_OWM_BASE,
+ .end = ASIC3_OWM_BASE + 0x13,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = ASIC3_IRQ_OWM,
+ .start = ASIC3_IRQ_OWM,
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+ },
+};
+
+static int ds1wm_enable(struct platform_device *pdev)
+{
+ struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
+
+ /* Turn on external clocks and the OWM clock */
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
+ msleep(1);
+
+ /* Reset and enable DS1WM */
+ asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
+ ASIC3_EXTCF_OWM_RESET, 1);
+ msleep(1);
+ asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
+ ASIC3_EXTCF_OWM_RESET, 0);
+ msleep(1);
+ asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
+ ASIC3_EXTCF_OWM_EN, 1);
+ msleep(1);
+
+ return 0;
+}
+
+static int ds1wm_disable(struct platform_device *pdev)
+{
+ struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
+
+ asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
+ ASIC3_EXTCF_OWM_EN, 0);
+
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
+
+ return 0;
+}
+
+static struct mfd_cell asic3_cell_ds1wm = {
+ .name = "ds1wm",
+ .enable = ds1wm_enable,
+ .disable = ds1wm_disable,
+ .driver_data = &ds1wm_pdata,
+ .num_resources = ARRAY_SIZE(ds1wm_resources),
+ .resources = ds1wm_resources,
+};
+
+static struct tmio_mmc_data asic3_mmc_data = {
+ .hclk = 24576000,
+};
+
+static struct resource asic3_mmc_resources[] = {
+ {
+ .start = ASIC3_SD_CTRL_BASE,
+ .end = ASIC3_SD_CTRL_BASE + 0x3ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = ASIC3_SD_CONFIG_BASE,
+ .end = ASIC3_SD_CONFIG_BASE + 0x1ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static int asic3_mmc_enable(struct platform_device *pdev)
+{
+ struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
+
+ /* Not sure if it must be done bit by bit, but leaving as-is */
+ asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
+ ASIC3_SDHWCTRL_LEVCD, 1);
+ asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
+ ASIC3_SDHWCTRL_LEVWP, 1);
+ asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
+ ASIC3_SDHWCTRL_SUSPEND, 0);
+ asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
+ ASIC3_SDHWCTRL_PCLR, 0);
+
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
+ /* CLK32 used for card detection and for interruption detection
+ * when HCLK is stopped.
+ */
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
+ msleep(1);
+
+ /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
+ asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
+ CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
+
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
+ asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
+ msleep(1);
+
+ asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
+ ASIC3_EXTCF_SD_MEM_ENABLE, 1);
+
+ /* Enable SD card slot 3.3V power supply */
+ asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
+ ASIC3_SDHWCTRL_SDPWR, 1);
+
+ return 0;
+}
+
+static int asic3_mmc_disable(struct platform_device *pdev)
+{
+ struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
+
+ /* Put in suspend mode */
+ asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
+ ASIC3_SDHWCTRL_SUSPEND, 1);
+
+ /* Disable clocks */
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
+ asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
+ return 0;
+}
+
+static struct mfd_cell asic3_cell_mmc = {
+ .name = "tmio-mmc",
+ .enable = asic3_mmc_enable,
+ .disable = asic3_mmc_disable,
+ .driver_data = &asic3_mmc_data,
+ .num_resources = ARRAY_SIZE(asic3_mmc_resources),
+ .resources = asic3_mmc_resources,
+};
+
+static int __init asic3_mfd_probe(struct platform_device *pdev,
+ struct resource *mem)
+{
+ struct asic3 *asic = platform_get_drvdata(pdev);
+ struct resource *mem_sdio;
+ int irq, ret;
+
+ mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!mem_sdio)
+ dev_dbg(asic->dev, "no SDIO MEM resource\n");
+
+ irq = platform_get_irq(pdev, 1);
+ if (irq < 0)
+ dev_dbg(asic->dev, "no SDIO IRQ resource\n");
+
+ /* DS1WM */
+ asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
+ ASIC3_EXTCF_OWM_SMB, 0);
+
+ ds1wm_resources[0].start >>= asic->bus_shift;
+ ds1wm_resources[0].end >>= asic->bus_shift;
+
+ asic3_cell_ds1wm.platform_data = &asic3_cell_ds1wm;
+ asic3_cell_ds1wm.data_size = sizeof(asic3_cell_ds1wm);
+
+ /* MMC */
+ asic3_mmc_resources[0].start >>= asic->bus_shift;
+ asic3_mmc_resources[0].end >>= asic->bus_shift;
+ asic3_mmc_resources[1].start >>= asic->bus_shift;
+ asic3_mmc_resources[1].end >>= asic->bus_shift;
+
+ asic3_cell_mmc.platform_data = &asic3_cell_mmc;
+ asic3_cell_mmc.data_size = sizeof(asic3_cell_mmc);
+
+ ret = mfd_add_devices(&pdev->dev, pdev->id,
+ &asic3_cell_ds1wm, 1, mem, asic->irq_base);
+ if (ret < 0)
+ goto out;
+
+ if (mem_sdio && (irq >= 0))
+ ret = mfd_add_devices(&pdev->dev, pdev->id,
+ &asic3_cell_mmc, 1, mem_sdio, irq);
+
+ out:
+ return ret;
+}
+
+static void asic3_mfd_remove(struct platform_device *pdev)
+{
+ mfd_remove_devices(&pdev->dev);
+}
/* Core */
static int __init asic3_probe(struct platform_device *pdev)
@@ -533,7 +830,6 @@ static int __init asic3_probe(struct platform_device *pdev)
struct asic3 *asic;
struct resource *mem;
unsigned long clksel;
- int map_size;
int ret = 0;
asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
@@ -553,8 +849,7 @@ static int __init asic3_probe(struct platform_device *pdev)
goto out_free;
}
- map_size = mem->end - mem->start + 1;
- asic->mapping = ioremap(mem->start, map_size);
+ asic->mapping = ioremap(mem->start, resource_size(mem));
if (!asic->mapping) {
ret = -ENOMEM;
dev_err(asic->dev, "Couldn't ioremap\n");
@@ -564,7 +859,7 @@ static int __init asic3_probe(struct platform_device *pdev)
asic->irq_base = pdata->irq_base;
/* calculate bus shift from mem resource */
- asic->bus_shift = 2 - (map_size >> 12);
+ asic->bus_shift = 2 - (resource_size(mem) >> 12);
clksel = 0;
asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
@@ -590,6 +885,13 @@ static int __init asic3_probe(struct platform_device *pdev)
goto out_irq;
}
+ /* Making a per-device copy is only needed for the
+ * theoretical case of multiple ASIC3s on one board:
+ */
+ memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
+
+ asic3_mfd_probe(pdev, mem);
+
dev_info(asic->dev, "ASIC3 Core driver\n");
return 0;
@@ -611,6 +913,8 @@ static int asic3_remove(struct platform_device *pdev)
int ret;
struct asic3 *asic = platform_get_drvdata(pdev);
+ asic3_mfd_remove(pdev);
+
ret = asic3_gpio_remove(pdev);
if (ret < 0)
return ret;
diff --git a/drivers/mfd/da903x.c b/drivers/mfd/da903x.c
index 7283d88..e5ffe56 100644
--- a/drivers/mfd/da903x.c
+++ b/drivers/mfd/da903x.c
@@ -561,7 +561,7 @@ static int __init da903x_init(void)
{
return i2c_add_driver(&da903x_driver);
}
-module_init(da903x_init);
+subsys_initcall(da903x_init);
static void __exit da903x_exit(void)
{
diff --git a/drivers/mfd/ezx-pcap.c b/drivers/mfd/ezx-pcap.c
new file mode 100644
index 0000000..671a7ef
--- /dev/null
+++ b/drivers/mfd/ezx-pcap.c
@@ -0,0 +1,505 @@
+/*
+ * Driver for Motorola PCAP2 as present in EZX phones
+ *
+ * Copyright (C) 2006 Harald Welte <laforge@openezx.org>
+ * Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mfd/ezx-pcap.h>
+#include <linux/spi/spi.h>
+
+#define PCAP_ADC_MAXQ 8
+struct pcap_adc_request {
+ u8 bank;
+ u8 ch[2];
+ u32 flags;
+ void (*callback)(void *, u16[]);
+ void *data;
+};
+
+struct pcap_adc_sync_request {
+ u16 res[2];
+ struct completion completion;
+};
+
+struct pcap_chip {
+ struct spi_device *spi;
+
+ /* IO */
+ u32 buf;
+ struct mutex io_mutex;
+
+ /* IRQ */
+ unsigned int irq_base;
+ u32 msr;
+ struct work_struct isr_work;
+ struct work_struct msr_work;
+ struct workqueue_struct *workqueue;
+
+ /* ADC */
+ struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
+ u8 adc_head;
+ u8 adc_tail;
+ struct mutex adc_mutex;
+};
+
+/* IO */
+static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)
+{
+ struct spi_transfer t;
+ struct spi_message m;
+ int status;
+
+ memset(&t, 0, sizeof t);
+ spi_message_init(&m);
+ t.len = sizeof(u32);
+ spi_message_add_tail(&t, &m);
+
+ pcap->buf = *data;
+ t.tx_buf = (u8 *) &pcap->buf;
+ t.rx_buf = (u8 *) &pcap->buf;
+ status = spi_sync(pcap->spi, &m);
+
+ if (status == 0)
+ *data = pcap->buf;
+
+ return status;
+}
+
+int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
+{
+ int ret;
+
+ mutex_lock(&pcap->io_mutex);
+ value &= PCAP_REGISTER_VALUE_MASK;
+ value |= PCAP_REGISTER_WRITE_OP_BIT
+ | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
+ ret = ezx_pcap_putget(pcap, &value);
+ mutex_unlock(&pcap->io_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(ezx_pcap_write);
+
+int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
+{
+ int ret;
+
+ mutex_lock(&pcap->io_mutex);
+ *value = PCAP_REGISTER_READ_OP_BIT
+ | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
+
+ ret = ezx_pcap_putget(pcap, value);
+ mutex_unlock(&pcap->io_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(ezx_pcap_read);
+
+/* IRQ */
+static inline unsigned int irq2pcap(struct pcap_chip *pcap, int irq)
+{
+ return 1 << (irq - pcap->irq_base);
+}
+
+int pcap_to_irq(struct pcap_chip *pcap, int irq)
+{
+ return pcap->irq_base + irq;
+}
+EXPORT_SYMBOL_GPL(pcap_to_irq);
+
+static void pcap_mask_irq(unsigned int irq)
+{
+ struct pcap_chip *pcap = get_irq_chip_data(irq);
+
+ pcap->msr |= irq2pcap(pcap, irq);
+ queue_work(pcap->workqueue, &pcap->msr_work);
+}
+
+static void pcap_unmask_irq(unsigned int irq)
+{
+ struct pcap_chip *pcap = get_irq_chip_data(irq);
+
+ pcap->msr &= ~irq2pcap(pcap, irq);
+ queue_work(pcap->workqueue, &pcap->msr_work);
+}
+
+static struct irq_chip pcap_irq_chip = {
+ .name = "pcap",
+ .mask = pcap_mask_irq,
+ .unmask = pcap_unmask_irq,
+};
+
+static void pcap_msr_work(struct work_struct *work)
+{
+ struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);
+
+ ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
+}
+
+static void pcap_isr_work(struct work_struct *work)
+{
+ struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
+ struct pcap_platform_data *pdata = pcap->spi->dev.platform_data;
+ u32 msr, isr, int_sel, service;
+ int irq;
+
+ ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
+ ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
+
+ /* We cant service/ack irqs that are assigned to port 2 */
+ if (!(pdata->config & PCAP_SECOND_PORT)) {
+ ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
+ isr &= ~int_sel;
+ }
+ ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
+
+ local_irq_disable();
+ service = isr & ~msr;
+
+ for (irq = pcap->irq_base; service; service >>= 1, irq++) {
+ if (service & 1) {
+ struct irq_desc *desc = irq_to_desc(irq);
+
+ if (WARN(!desc, KERN_WARNING
+ "Invalid PCAP IRQ %d\n", irq))
+ break;
+
+ if (desc->status & IRQ_DISABLED)
+ note_interrupt(irq, desc, IRQ_NONE);
+ else
+ desc->handle_irq(irq, desc);
+ }
+ }
+ local_irq_enable();
+}
+
+static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct pcap_chip *pcap = get_irq_data(irq);
+
+ desc->chip->ack(irq);
+ queue_work(pcap->workqueue, &pcap->isr_work);
+ return;
+}
+
+/* ADC */
+static void pcap_disable_adc(struct pcap_chip *pcap)
+{
+ u32 tmp;
+
+ ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
+ tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);
+ ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
+}
+
+static void pcap_adc_trigger(struct pcap_chip *pcap)
+{
+ u32 tmp;
+ u8 head;
+
+ mutex_lock(&pcap->adc_mutex);
+ head = pcap->adc_head;
+ if (!pcap->adc_queue[head]) {
+ /* queue is empty, save power */
+ pcap_disable_adc(pcap);
+ mutex_unlock(&pcap->adc_mutex);
+ return;
+ }
+ mutex_unlock(&pcap->adc_mutex);
+
+ /* start conversion on requested bank */
+ tmp = pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;
+
+ if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
+ tmp |= PCAP_ADC_AD_SEL1;
+
+ ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
+ ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
+}
+
+static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
+{
+ struct pcap_chip *pcap = _pcap;
+ struct pcap_adc_request *req;
+ u16 res[2];
+ u32 tmp;
+
+ mutex_lock(&pcap->adc_mutex);
+ req = pcap->adc_queue[pcap->adc_head];
+
+ if (WARN(!req, KERN_WARNING "adc irq without pending request\n"))
+ return IRQ_HANDLED;
+
+ /* read requested channels results */
+ ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
+ tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);
+ tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
+ tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
+ ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
+ ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
+ res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
+ res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;
+
+ pcap->adc_queue[pcap->adc_head] = NULL;
+ pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
+ mutex_unlock(&pcap->adc_mutex);
+
+ /* pass the results and release memory */
+ req->callback(req->data, res);
+ kfree(req);
+
+ /* trigger next conversion (if any) on queue */
+ pcap_adc_trigger(pcap);
+
+ return IRQ_HANDLED;
+}
+
+int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
+ void *callback, void *data)
+{
+ struct pcap_adc_request *req;
+
+ /* This will be freed after we have a result */
+ req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
+ if (!req)
+ return -ENOMEM;
+
+ req->bank = bank;
+ req->flags = flags;
+ req->ch[0] = ch[0];
+ req->ch[1] = ch[1];
+ req->callback = callback;
+ req->data = data;
+
+ mutex_lock(&pcap->adc_mutex);
+ if (pcap->adc_queue[pcap->adc_tail]) {
+ mutex_unlock(&pcap->adc_mutex);
+ kfree(req);
+ return -EBUSY;
+ }
+ pcap->adc_queue[pcap->adc_tail] = req;
+ pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
+ mutex_unlock(&pcap->adc_mutex);
+
+ /* start conversion */
+ pcap_adc_trigger(pcap);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pcap_adc_async);
+
+static void pcap_adc_sync_cb(void *param, u16 res[])
+{
+ struct pcap_adc_sync_request *req = param;
+
+ req->res[0] = res[0];
+ req->res[1] = res[1];
+ complete(&req->completion);
+}
+
+int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
+ u16 res[])
+{
+ struct pcap_adc_sync_request sync_data;
+ int ret;
+
+ init_completion(&sync_data.completion);
+ ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
+ &sync_data);
+ if (ret)
+ return ret;
+ wait_for_completion(&sync_data.completion);
+ res[0] = sync_data.res[0];
+ res[1] = sync_data.res[1];
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pcap_adc_sync);
+
+/* subdevs */
+static int pcap_remove_subdev(struct device *dev, void *unused)
+{
+ platform_device_unregister(to_platform_device(dev));
+ return 0;
+}
+
+static int __devinit pcap_add_subdev(struct pcap_chip *pcap,
+ struct pcap_subdev *subdev)
+{
+ struct platform_device *pdev;
+
+ pdev = platform_device_alloc(subdev->name, subdev->id);
+ pdev->dev.parent = &pcap->spi->dev;
+ pdev->dev.platform_data = subdev->platform_data;
+ platform_set_drvdata(pdev, pcap);
+
+ return platform_device_add(pdev);
+}
+
+static int __devexit ezx_pcap_remove(struct spi_device *spi)
+{
+ struct pcap_chip *pcap = dev_get_drvdata(&spi->dev);
+ struct pcap_platform_data *pdata = spi->dev.platform_data;
+ int i, adc_irq;
+
+ /* remove all registered subdevs */
+ device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
+
+ /* cleanup ADC */
+ adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
+ PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
+ free_irq(adc_irq, pcap);
+ mutex_lock(&pcap->adc_mutex);
+ for (i = 0; i < PCAP_ADC_MAXQ; i++)
+ kfree(pcap->adc_queue[i]);
+ mutex_unlock(&pcap->adc_mutex);
+
+ /* cleanup irqchip */
+ for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
+ set_irq_chip_and_handler(i, NULL, NULL);
+
+ destroy_workqueue(pcap->workqueue);
+
+ kfree(pcap);
+
+ return 0;
+}
+
+static int __devinit ezx_pcap_probe(struct spi_device *spi)
+{
+ struct pcap_platform_data *pdata = spi->dev.platform_data;
+ struct pcap_chip *pcap;
+ int i, adc_irq;
+ int ret = -ENODEV;
+
+ /* platform data is required */
+ if (!pdata)
+ goto ret;
+
+ pcap = kzalloc(sizeof(*pcap), GFP_KERNEL);
+ if (!pcap) {
+ ret = -ENOMEM;
+ goto ret;
+ }
+
+ mutex_init(&pcap->io_mutex);
+ mutex_init(&pcap->adc_mutex);
+ INIT_WORK(&pcap->isr_work, pcap_isr_work);
+ INIT_WORK(&pcap->msr_work, pcap_msr_work);
+ dev_set_drvdata(&spi->dev, pcap);
+
+ /* setup spi */
+ spi->bits_per_word = 32;
+ spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
+ ret = spi_setup(spi);
+ if (ret)
+ goto free_pcap;
+
+ pcap->spi = spi;
+
+ /* setup irq */
+ pcap->irq_base = pdata->irq_base;
+ pcap->workqueue = create_singlethread_workqueue("pcapd");
+ if (!pcap->workqueue) {
+ dev_err(&spi->dev, "cant create pcap thread\n");
+ goto free_pcap;
+ }
+
+ /* redirect interrupts to AP, except adcdone2 */
+ if (!(pdata->config & PCAP_SECOND_PORT))
+ ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
+ (1 << PCAP_IRQ_ADCDONE2));
+
+ /* setup irq chip */
+ for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
+ set_irq_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
+ set_irq_chip_data(i, pcap);
+#ifdef CONFIG_ARM
+ set_irq_flags(i, IRQF_VALID);
+#else
+ set_irq_noprobe(i);
+#endif
+ }
+
+ /* mask/ack all PCAP interrupts */
+ ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
+ ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
+ pcap->msr = PCAP_MASK_ALL_INTERRUPT;
+
+ set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
+ set_irq_data(spi->irq, pcap);
+ set_irq_chained_handler(spi->irq, pcap_irq_handler);
+ set_irq_wake(spi->irq, 1);
+
+ /* ADC */
+ adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
+ PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
+
+ ret = request_irq(adc_irq, pcap_adc_irq, 0, "ADC", pcap);
+ if (ret)
+ goto free_irqchip;
+
+ /* setup subdevs */
+ for (i = 0; i < pdata->num_subdevs; i++) {
+ ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
+ if (ret)
+ goto remove_subdevs;
+ }
+
+ /* board specific quirks */
+ if (pdata->init)
+ pdata->init(pcap);
+
+ return 0;
+
+remove_subdevs:
+ device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
+/* free_adc: */
+ free_irq(adc_irq, pcap);
+free_irqchip:
+ for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
+ set_irq_chip_and_handler(i, NULL, NULL);
+/* destroy_workqueue: */
+ destroy_workqueue(pcap->workqueue);
+free_pcap:
+ kfree(pcap);
+ret:
+ return ret;
+}
+
+static struct spi_driver ezxpcap_driver = {
+ .probe = ezx_pcap_probe,
+ .remove = __devexit_p(ezx_pcap_remove),
+ .driver = {
+ .name = "ezx-pcap",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init ezx_pcap_init(void)
+{
+ return spi_register_driver(&ezxpcap_driver);
+}
+
+static void __exit ezx_pcap_exit(void)
+{
+ spi_unregister_driver(&ezxpcap_driver);
+}
+
+module_init(ezx_pcap_init);
+module_exit(ezx_pcap_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
+MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
diff --git a/drivers/mfd/pcf50633-core.c b/drivers/mfd/pcf50633-core.c
index 082c197..8d3c38b 100644
--- a/drivers/mfd/pcf50633-core.c
+++ b/drivers/mfd/pcf50633-core.c
@@ -705,5 +705,5 @@ MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 PMU");
MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
MODULE_LICENSE("GPL");
-module_init(pcf50633_init);
+subsys_initcall(pcf50633_init);
module_exit(pcf50633_exit);
diff --git a/drivers/mfd/pcf50633-gpio.c b/drivers/mfd/pcf50633-gpio.c
index 2fa2eca..9ab19a8 100644
--- a/drivers/mfd/pcf50633-gpio.c
+++ b/drivers/mfd/pcf50633-gpio.c
@@ -15,6 +15,7 @@
*/
#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/mfd/pcf50633/core.h>
#include <linux/mfd/pcf50633/gpio.h>
@@ -116,3 +117,5 @@ int pcf50633_gpio_power_supply_set(struct pcf50633 *pcf,
return pcf50633_reg_set_bit_mask(pcf, reg, mask, val);
}
EXPORT_SYMBOL_GPL(pcf50633_gpio_power_supply_set);
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/t7l66xb.c b/drivers/mfd/t7l66xb.c
index 875f7a8..0a255c1 100644
--- a/drivers/mfd/t7l66xb.c
+++ b/drivers/mfd/t7l66xb.c
@@ -108,7 +108,7 @@ static int t7l66xb_mmc_disable(struct platform_device *mmc)
/*--------------------------------------------------------------------------*/
-static const struct tmio_mmc_data t7166xb_mmc_data = {
+static struct tmio_mmc_data t7166xb_mmc_data = {
.hclk = 24000000,
};
diff --git a/drivers/mfd/tc6387xb.c b/drivers/mfd/tc6387xb.c
index c3993ac..3280ab33 100644
--- a/drivers/mfd/tc6387xb.c
+++ b/drivers/mfd/tc6387xb.c
@@ -75,7 +75,7 @@ static int tc6387xb_mmc_disable(struct platform_device *mmc)
/*--------------------------------------------------------------------------*/
-const static struct tmio_mmc_data tc6387xb_mmc_data = {
+static struct tmio_mmc_data tc6387xb_mmc_data = {
.hclk = 24000000,
};
diff --git a/drivers/mfd/tc6393xb.c b/drivers/mfd/tc6393xb.c
index 9d2abb5..1429a73 100644
--- a/drivers/mfd/tc6393xb.c
+++ b/drivers/mfd/tc6393xb.c
@@ -136,7 +136,7 @@ static int tc6393xb_nand_enable(struct platform_device *nand)
return 0;
}
-const static struct tmio_mmc_data tc6393xb_mmc_data = {
+static struct tmio_mmc_data tc6393xb_mmc_data = {
.hclk = 24000000,
};
diff --git a/drivers/mfd/twl4030-core.c b/drivers/mfd/twl4030-core.c
index ec90e95..cd1008c 100644
--- a/drivers/mfd/twl4030-core.c
+++ b/drivers/mfd/twl4030-core.c
@@ -647,7 +647,7 @@ static inline int __init unprotect_pm_master(void)
return e;
}
-static void __init clocks_init(struct device *dev)
+static void clocks_init(struct device *dev)
{
int e = 0;
struct clk *osc;
diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index aca2670..bae61b2 100644
--- a/drivers/mfd/twl4030-irq.c
+++ b/drivers/mfd/twl4030-irq.c
@@ -255,7 +255,7 @@ static int twl4030_irq_thread(void *data)
* thread. All we do here is acknowledge and mask the interrupt and wakeup
* the kernel thread.
*/
-static void handle_twl4030_pih(unsigned int irq, irq_desc_t *desc)
+static void handle_twl4030_pih(unsigned int irq, struct irq_desc *desc)
{
/* Acknowledge, clear *AND* mask the interrupt... */
desc->chip->ack(irq);
diff --git a/drivers/mfd/wm8350-regmap.c b/drivers/mfd/wm8350-regmap.c
index 9a4cc95..7ccc1ea 100644
--- a/drivers/mfd/wm8350-regmap.c
+++ b/drivers/mfd/wm8350-regmap.c
@@ -3186,7 +3186,7 @@ const struct wm8350_reg_access wm8350_reg_io_map[] = {
/* read write volatile */
{ 0xFFFF, 0xFFFF, 0xFFFF }, /* R0 - Reset/ID */
{ 0x7CFF, 0x0C00, 0x7FFF }, /* R1 - ID */
- { 0x0000, 0x0000, 0x0000 }, /* R2 */
+ { 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */
{ 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */
{ 0xFEF7, 0xFEF7, 0xF800 }, /* R4 - System Control 2 */
{ 0x80FF, 0x80FF, 0x8000 }, /* R5 - System Hibernate */
@@ -3411,7 +3411,7 @@ const struct wm8350_reg_access wm8350_reg_io_map[] = {
{ 0x0000, 0x0000, 0x0000 }, /* R224 */
{ 0x8F3F, 0x0000, 0xFFFF }, /* R225 - DCDC/LDO status */
{ 0x0000, 0x0000, 0xFFFF }, /* R226 - Charger status */
- { 0x0000, 0x0000, 0xFFFF }, /* R227 */
+ { 0x34FE, 0x0000, 0xFFFF }, /* R227 */
{ 0x0000, 0x0000, 0x0000 }, /* R228 */
{ 0x0000, 0x0000, 0x0000 }, /* R229 */
{ 0xFFFF, 0x1FFF, 0xFFFF }, /* R230 - GPIO Pin Status */
diff --git a/drivers/mfd/wm8400-core.c b/drivers/mfd/wm8400-core.c
index 7c21bf7..ecfc8bb 100644
--- a/drivers/mfd/wm8400-core.c
+++ b/drivers/mfd/wm8400-core.c
@@ -460,7 +460,7 @@ static int __init wm8400_module_init(void)
return ret;
}
-module_init(wm8400_module_init);
+subsys_initcall(wm8400_module_init);
static void __exit wm8400_module_exit(void)
{
generated by cgit v0.10.2 at 2024-11-20 17:55:41 (GMT)