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b4420 and b4860 device trees do not have these properties.
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit 4f6d45d7db7e4622a74b9fd8c99b13c68129d70d)
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On Book3E some SPE/FP/AltiVec interrupts share the same number. Use
common defines to indentify these numbers.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
[scottwood@freescale.com: fixed space-before-tab]
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit c58ce397a62ec14b7b06c407a4173ed667e20d5f)
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On Book3E some SPE/FP/AltiVec interrupts share the same number. Use
common defines to indentify these numbers.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit 6b310fc58db27318309a04621d3a4509f1c7845a)
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For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO EISR bit value
of error interrupt in dts node.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit 0e3d4373b8a7757a8f5187f5cabafb6aceff469b)
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as per controller description,
"While programming a NAND flash, status read should never skipped.
Because it may happen that a new command is issued to the NAND Flash,
even when the device has not yet finished processing the previous request.
This may result in unpredictable behaviour."
IFC controller never polls for R/B signal after command send. It just return
control to software. This behaviour may not occur with NAND flash access.
because new commands are sent after polling R/B signal. But it may happen
in scenario where GPCM-ASIC and NAND flash device are working simultaneously.
Update the controller driver to take care of this requirement
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit 4af9874916b14db407bee18590fe1847f541c2e2)
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Current IFC driver supports till 4K page size NAND flash.
Add support of 8K Page size NAND flash
- Add nand_ecclayout for 4 bit & 8 bit ecc
- Defines constants
- also fix ecc.strength for 8bit ecc of 8K page size NAND
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit ebff90b288c347f3af1b3d164c258aeb2bed60ec)
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And in flush_hugetlb_page(), don't check whether vma is NULL after
we've already dereferenced it.
This was found by Dan using static analysis as described here:
https://lists.ozlabs.org/pipermail/linuxppc-dev/2013-November/113161.html
We currently get away with this because the callers that currently pass
NULL for vma seem to be 32-bit-only (e.g. highmem, and
CONFIG_DEBUG_PGALLOC in pgtable_32.c) Hugetlb is currently 64-bit only,
so we never saw a NULL vma here.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
(cherry picked from commit d742aa152f27448d39ce65fb829e396d10cd63a9)
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Commit 9863c28a2af90a56c088f5f6288d7f6d2c923c14 ("powerpc: Emulate sync
instruction variants") introduced a build breakage with
CONFIG_PPC_EMULATED_STATS enabled.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Kumar Gala <galak@kernel.org>
Cc: James Yang <James.Yang@freescale.com>
---
(cherry picked from commit a3821b2af185b64e3382c45fbdaa2cbc91ce14b8)
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Reserved fields of the sync instruction have been used for other
instructions (e.g. lwsync). On processors that do not support variants
of the sync instruction, emulate it by executing a sync to subsume the
effect of the intended instruction.
Signed-off-by: James Yang <James.Yang@freescale.com>
[scottwood@freescale.com: whitespace and subject line fix]
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit 9863c28a2af90a56c088f5f6288d7f6d2c923c14)
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Otherwise, we get a debug traceback due to the use of
smp_processor_id() (or get_paca()) inside hard_smp_processor_id().
mpic_host_map() is just looking for a default CPU, so it doesn't matter
if we migrate after getting the CPU ID.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
(cherry picked from commit 32dda05f4ec2b854b594bd91590c46c5197d77e1)
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Enable CONFIG_AT803X_PHY to support AR8030/8033/8035 PHY.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit 788d399d3c3dd1e02ab316272e1dc1881182e16d)
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If CONFIG_ALTIVEC is enabled for CoreNet64, and if we also
select CONFIG_E{5,6}500_CPU this may introduce -mcpu=e500mc64
into $CFLAGS. But Altivec option not allowed with e500mc64,
then some compiling errors occur like this:
CC arch/powerpc/lib/xor_vmx.o
arch/powerpc/lib/xor_vmx.c:1:0: error: AltiVec not supported in this target
make[1]: *** [arch/powerpc/lib/xor_vmx.o] Error 1
make: *** [arch/powerpc/lib] Error 2
So we should restrict e500mc64 in altivec scenario.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit cbf8a358be27ceecea5bd44cf82ab01683fcc90c)
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The P1010RDB-PB is similar to P1010RDB(P1010RDB-PA).
So, P1010RDB-PB use the same platform file as P1010RDB.
Then Add support for P1010RDB-PB platform.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit fd1348d098b5d0f633c869b50a74cfcbeb9834f5)
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B4860EMU is a emualtor target with minimum peripherals. It is based on
B4860QDS and trimmed down most peripherals due to either not modeled or
lack of board level connections. The main purpose of this minimum dts is
to speed up booting on emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
[scottwood@freescale.com: whitespace fix]
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit 312325031d0da8a7c4b2857e79a23fb89df2b887)
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T4240EMU is an emulator target with minimum peripherals. It is based on
T4240QDS and trimmed down most peripherals due to either not modeled or
lack of board level connections. The main purpose of this minimum dts is
to speed up booting on emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
[scottwood@freescale.com: whitespace fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit 8f4af7df86c793fe3333e0cd2c769beef912d21c)
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Currently all these boards use the same machine struct and also select
the same kernel options, so it seems a bit of redundant to keep one
separate kernel option for each board. Also update the defconfigs
according to this change.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit 9e0967572e5a0e8c887b2d71192bdad342e8a3dd)
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This file is also used by some RDB and QDS boards. So the name seems
not so accurate. Rename it to corenet_generic.c. Also update the
function names in this file according to the change.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
(cherry picked from commit befe7c123ee4546316bb9aa9952c0e2f7c0d9c48)
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In the current kernel, the board files for p2041rdb, p3041ds, p4080ds,
p5020ds, p5040ds, t4240qds and b4qds are almost the same except the
machine name. So this introduces a cornet_generic machine to support
all these boards to avoid the code duplication.
With these changes the file corenet_ds.h becomes useless. Just delete
it.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
(cherry picked from commit 512e267f3594b5a3b4937a00666241cb994ef55a)
Conflicts:
arch/powerpc/platforms/85xx/b4_qds.c
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In order for supported SoCs to enter deepsleep the QBMan ip blocks must not
have any pending interrupt status bits set in the Portals.
Therefore, in the pm callbacks for each portal, save the isdr, and clear the isr.
On the resume side, reset the save isdr.
Also fix the buffer pool depletion notification in all bman portals.
The default value is to notify them. This is an issue for unused portals, as
the portal will have the corresponding isr bit set and will prevent deepsleep
for occuring.
The unused portals need to have their ISDR and ISR cleared in order for
the qman block to enter idle state.
Also re-added the setting of ISDR clear ISR for the qbman ccsr block.
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Change-Id: Icd908215ed10d39e3f112b939c4d6b2758a97a76
Reviewed-on: http://git.am.freescale.net:8181/10717
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com>
Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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This additional parameter (window number) is required based
on the latest update of pamu driver.
Signed-off-by: Vakul Garg <vakul@freescale.com>
Change-Id: I14a4d61c6f6790aa87ce5924bb9893d9170e8a76
Reviewed-on: http://git.am.freescale.net:8181/10719
Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Set the register IPPDEXPCR (IP Powerdown Exception Control Register) to
enable IP blocks which work as wakeup source when sleep/deep sleep.
Change-Id: Id95cb920cab90e12851995d039bd866e6388f8ae
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10711
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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"fsl,p104xrdb-cpld" -> "fsl,t104xrdb-cpld"
Change-Id: I30d83d1867022485008b48c3d7d601040b840621
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10710
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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T104x has deep sleep feature, which can switch off most parts of
the SoC when it is in deep sleep mode. This way, it becomes more
energy-efficient.
The DDR controller will also be powered off in deep sleep. Therefore,
the last stage (the latter part of fsl_dp_enter_low) will run without DDR
access. This piece of code and related TLBs are prefetched in advance.
Due to the different initialization code between 32-bit and 64-bit, they
have seperate resume entry and precedure.
The feature supports 32-bit and 64-bit kernel mode.
Change-Id: I9b9b9188fdc67167030658b6cc1d0a1cbe7e2180
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10709
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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In the last stage of deep sleep, software will trigger a Finite
State Machine (FSM) to control the hardware precedure, such as
board isolation, killing PLLs, removing power, and so on.
When the system is waked up by an interrupt, the FSM controls the
hardware to complete the early resume precedure.
This patch configure the EPU FSM preparing for deep sleep.
Change-Id: I42b196a656324260c1d1cfcf688016c6f8d7ebe8
Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10708
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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In sleep mode, the clocks of e500 cores and unused IP blocks is
turned off. The IP blocks which are allowed to wake up the processor
are still running.
The sleep mode is equal to the Standby state in Linux. Use the
command to enter sleep mode:
echo standby > /sys/power/state
Change-Id: I1cf82fddc34a9c0ad3cb66ae554e5521805365e6
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10707
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.
The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.
There are two versions of register map in RCPM, which is specified by
the compatible entry in the RCPM node of device tree.
Change-Id: I113211311c7241df95f067103d0ed81ada26d2ed
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10706
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback function will flush all caches in the current cpu.
Change-Id: Id6da30ac5490cac5f5669909df2152f0ee952086
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10705
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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In 64-bit mode, kernel just clears the irq soft-enable flag
in struct paca_struct to disable external irqs. But, in
the case of suspend, irqs should be disabled by hardware.
Therefore, use hard_irq_disable() instead of local_irq_disable().
Change-Id: I743ec4971a9e1a9b5a3c2b463324588d48af65af
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10704
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Change-Id: I30aa0bc40fcbe8d6abb2511dbf7bfb31397078e6
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10643
Reviewed-by: Nir Erez <nir.erez@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
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Change-Id: I26fd2c48e2dbb680e51cf5abdea5345f7e2694be
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10642
Reviewed-by: Eyal Harari <Eyal.Harari@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Multiply the number of work queues by the number of 802.1p PFC
priorities.
With this patch, egress traffic can be classiffied on different work
queues depending on the skb priority.
Each work queue can be paused by a PFC priority.
When the private interfaces' buffer pool depletes, PFC frames are
issued with all configured priorities set in the Class-Enable Vector.
Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com>
Change-Id: Ibaf928e547c662dacf08063bd94953b9cf6138e0
Reviewed-on: http://git.am.freescale.net:8181/10498
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
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As PFC support is in the experimental phase, the default number of
Classes of Service is set to a minimum of 3.
Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com>
Change-Id: I5a2848788617a00cd72f2db51febcb4023a9bef5
Reviewed-on: http://git.am.freescale.net:8181/10652
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Reviewed-by: Ehud Shiff <Ehud.Shiff@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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The BMan Pool Depletion Register (FMBM_RMPD) has 8 bits for
- NBPDE - Buffer Pools Depleted Enable
- QbbPEV - 802.1Qbb Priority Enable Vector
- SBPD - Single Buffer Pool Depletion
This patch takes into account all the 8 bits for each of these fields.
Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com>
Change-Id: Ie373c6b12501b7005233095ca480fb1bdad57416
Reviewed-on: http://git.am.freescale.net:8181/10606
Reviewed-by: Ehud Shiff <Ehud.Shiff@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
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Change-Id: I0058a7152ec34038961bdfb7598d280b7ec47777
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10411
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
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Change-Id: I5614f271b89f912553e9a6558c4256c7c54ba6e8
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10410
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
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This patch avoids modifying the structures defined in 'fm_ext.h' and
configures all PFC buffer pool depletion parameters in
'CheckNConfigFmPortAdvArgs', between 'FM_PORT_Config' and
'FM_PORT_Init'.
Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com>
Change-Id: I7268fa71416cb25f0cb42b56cd89a702996801fa
Reviewed-on: http://git.am.freescale.net:8181/10605
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
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The SDK no longer supports rev1.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: Ief0e72d5305b16f994df3beca58134dd96e8aff7
Reviewed-on: http://git.am.freescale.net:8181/10273
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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The SDK no longer supports e6500 rev1.
This reverts commit 38043080bb90f931efbe56a3f407c18206985f18
"powerpc/e6500: extend TLB miss lock to invalidations"
and commit b9e282e1347b771b736a84e6b0a1048c551e6a6c
"powerpc/e6500: add kconfig option for erratum A-004801"
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: I749f497cbb6b96d045434065b869b253f01d6575
Reviewed-on: http://git.am.freescale.net:8181/10272
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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This reverts commit f4c0e693ccc3422c5b809e7cc8f59b7637e3b7ab.
rev1 is no longer supported in the SDK, and the workaround for A-006198
conflicts with machine check support.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: I64e1ce19eb59a6bba8649156597cc49ff9b62b1e
Reviewed-on: http://git.am.freescale.net:8181/10271
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Add device-id entry for N25Q512A in device_id structure.
Flash has following features:
-64MB size, 1.8V, Mulitple I/O, 4KB Sector erase memory.
-Memory is organised as 1024(64KB) main sectors.
-Each sector is divided into 256 pages.
-Register set/Opcodes are similar to other N25Q family products
-Device ID: 20ba20
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Change-Id: Ifd191e1f2b0fb94ad7f37ff08dbf60f8e1617991
Reviewed-on: http://git.am.freescale.net:8181/10594
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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| drivers/uio/fsl_sec_uio.c: In function 'fsl_sec_jr_probe':
| drivers/uio/fsl_sec_uio.c:186:2: error: implicit declaration of function 'of_address_to_resource' [-Werror=implicit-function-declaration]
| ret = of_address_to_resource(jr_node, 0, ®s);
| ^
| drivers/uio/fsl_sec_uio.c:211:2: error: implicit declaration of function 'irq_of_parse_and_map' [-Werror=implicit-function-declaration]
| jr->irq = irq_of_parse_and_map(jr_node, 0);
| ^
| drivers/uio/fsl_sec_uio.c: In function 'fsl_sec_probe':
| drivers/uio/fsl_sec_uio.c:296:2: error: implicit declaration of function 'of_iomap' [-Werror=implicit-function-declaration]
| sec_dev->global_regs = of_iomap(sec_node, 0);
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Change-Id: I5bcaa4e15c48c7aa80edb478ac86ad1aa6f2eea4
Reviewed-on: http://git.am.freescale.net:8181/10591
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Once the PCIe device assigned to a guest VM (via VFIO) gets detached from the iommu domain
(when guest terminates), its PAMU table entry is disabled. So, this would prevent the device
from being used once it's assigned back to the host.
This patch allows for creation of a default DMA window corresponding to the device
and subsequently enabling the PAMU table entry. Before we enable the entry, we ensure that
the device's bus master capability is disabled (device quiesced).
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: Iab4da4adfac8536a6834011431a395ba3a4982d2
Reviewed-on: http://git.am.freescale.net:8181/10257
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Factor out PCI specific code in the PAMU driver.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: Ia6d73dca46b7274e14f7d7099aaef22d6510d1aa
Reviewed-on: http://git.am.freescale.net:8181/10256
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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If a process explictly unmapped DMA fragments the reference
count of each fragement wasn't properly decremented causing
a leak. This would only occur if the proccess explicitly
umapped the memory, exiting the process did correctly adjust
the reference counts
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Change-Id: Ia9adfccd5249d17d5506796b1fe71c32f46cab30
Reviewed-on: http://git.am.freescale.net:8181/10527
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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asf_gianfar will compile only when CONFIG_GIANFAR
and CONFIG_AS_FASTPATH are set.
Replacing CONFIG_RX_TX_BUFF_XCHG with CONFIG_AS_FASTPATH
and CONFIG_GIANFAR in skbuff structure of skbuff.h
Removing CONFIG_RX_TX_BUFF_XCHG flag from kconfig.
Change-Id: Iba0da980dfb807808cb3f9cd7d18a0229fa96b35
CR:ENGR00306399
Signed-off-by: Alok Makhariya <B46187@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10535
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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So far the DIU driver does not have a mechanism to do the
board specific initialization. So on some platforms,
such as P1022, 8610 and 5121, The board specific initialization
is implmented in the platform file such p10222_ds.
Actually, the DIU is already intialized in the u-boot, the pin sharing
and the signal routing are also set in u-boot. So we can leverage that
in kernel driver to avoid board sepecific initialization, especially
for the corenet platform, which is the abstraction for serveral
platfroms.
The potential problem is that when the system wakeup from the deep
sleep, some platform settings may need to be re-initialized. The CPLD
and FPGA settings will be kept, but the pixel clock register which
usually locate at the global utility space need to be reinitialized.
Generally, the pixel clock setting was implemented in the platform
file, But the pixel clock register itself should be part of the DIU
module, And for P1022,8610 and T1040, the pixel clock register have the
same structure, So we can consider to move the pixel clock setting
from the platform to the diu driver. This patch provide the options
set the pixel clock in the diu driver. But the original platform pixel
clock setting stil can be used for P1022,8610 and 512x without any
update. To implement the pixel clock setting in the diu driver. the
following update in the diu dts node was needed.
display:display@180000 {
compatible = "fsl,t1040-diu", "fsl,diu";
- reg = <0x180000 1000>;
+ reg = <0x180000 1000 0xfc028 4>;
pixclk = <0 255 0>;
interrupts = <74 2 0 0>;
}
The 0xfc028 is the offset for pixel clock register. the 3 segment of
the pixclk stand for the PXCKDLYDIR, the max of PXCK and the
PXCKDLY which will be used by the pixel clock register setting.
This was tested on T1040 platform. For other platform, the original
node together with the platform settings still can work.
The binding update also included in this patch.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Change-Id: I0663914b08378fc7852eab788801f4e5dc59977d
Reviewed-on: http://git.am.freescale.net:8181/10327
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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This driver config the L2 Cache to be SRAM mode and map the SRAM to user
space. The size and the address of SRAM are passed in the U-boot command
line as format: cache-sram=addr,size.
Please notice that this driver is exclusive with config FSL_85XX_CACHE_SRAM.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Change-Id: Ib0433acd459413fec5f5218751b0db79309895fd
Reviewed-on: http://git.am.freescale.net:8181/10295
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Po Liu <Po.Liu@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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For deep sleep, the diu module will power off, when wake up from the deep
sleep, more registers need to be reinitialized.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Change-Id: I3cffa545171a27391de0352aadcb871bc459e9dc
Reviewed-on: http://git.am.freescale.net:8181/10328
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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The USDPAA DMA freespace calculation should only count
segments with a reference count of zero as free
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Change-Id: Ib8752f8ad6cb4179b371b6480f47e84033260efe
Reviewed-on: http://git.am.freescale.net:8181/10526
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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