| Age | Commit message (Collapse) | Author |
|---|
|
The kernel space PCD part provides hash based outgoing traffic
distribution. The sources can be L2 MAC/L3 SRC and DST IP addr/
L4 SRC and DST port information. Current version only support
L2 information hash which is the default transmit policy in the
Linux bonding driver.
Signed-off-by: Jianhua Xie <jianhua.xie@freescale.com>
Change-Id: Ifd85630ab0eebd77713574f6cf51fb92203a1c06
Reviewed-on: http://git.am.freescale.net:8181/10414
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jiafei Pan <Jiafei.Pan@freescale.com>
Reviewed-by: Florinel Iordache <Florin.Iordache@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Linux bonding driver provides a method for aggregating multiple network
interface controllers (NICs) into a single logical bonded interface of
two or more so called (NIC) slaves. Slave selection for outgoing traffic
is done according to the transmit hash policy, which may be changed from
the default simple XOR policy via the xmit_hash_policy option. This
selection algorithm in Linux bonding driver is based on software.
The QorIQ Data Path Acceleration Architecture (DPAA) is a comprehensive
architecture which integrates all aspects of packet processing in the
SoC, addressing issues and requirements resulting from the multicore
nature of QorIQ SoCs. The DPAA includes Cores, Network and packet I/O,
Hardware offload accelerators. Hardware offload accelerators include
FMan/BMan/QMan and etc.
Offline port is one of FMan elements, which supports (Parse, Classify,
Distribute) PCD function on frames extracted frame descriptor (FD).
Offline port also can inspect traffic, split it into FQs on ingress, and
send traffic from the FQs to the interface on egress by the PCD function.
These patches are enhancing Linux kernel LAG (Link Aggregation) with
Freescale DPAA value added. The main idea is to utilize offline ports
with PCD function to help to distribute outgoing traffics, including
outgoing slaves device searching and selection. In another world,
patches are using CRC-64 based hashing of Keygen/scheme and the parser
result of outgoing frames header information to distribute outgoing
frames.
Beside of above, after integration this HW based LAG with Freescale
CEETMQos, these two features can support hardware based Qos for bundles
links rather than individual links.
These patches mainly include 2 parts:
'glue logic' and 'kernel space PCD'.
The glue logic first probes all available offline ports information via
reading dts, including tx fqid/default fqid/errors fqid, pcd fqs, other
private data pointer of offline ports for future reusing. The glue logic
also creates frames from skb and then sends these frames to offline port
directly, this offline port will continue to distribution frames from
the PCD FQs to the slave interface on egress by the PCD function, rather
than select slave device by CPU, neither make slave device driver create
frame from skb, nor make slave devices driver send frames.
These patches are supporting the mapping among offline ports and
available bundles at run-time. PCD based outgoing traffic distribution
can be enabled or disabled at run-time by sysfs interface in patches.
To do:
1. PCD policy L23/L34 have not been veryfied.
2. offline port buffer pool/buffer layout will be enhanced.
3. software based L4 csum for now, offline port based L4 csum need be fixed.
To test this HW based LAG after booting up Linux:
cd /sys/class/net/bond0/bonding/
echo 4 >mode
cat offline_ports
echo fman0-oh@1 > oh_needed_for_hw_distribution
cat oh_needed_for_hw_distribution
cat oh_en
echo 1 >oh_en
cat oh_en
echo +fm1-gb0 >slaves
echo +fm1-gb1 >slaves
ifconfig bond0 192.168.10.2/24 up
ping 192.168.10.1 -c 5
Signed-off-by: Jianhua Xie <jianhua.xie@freescale.com>
Change-Id: I3a6664bfcc9ec9ca3f86a5e36381220c5fcb07cf
Reviewed-on: http://git.am.freescale.net:8181/10413
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jiafei Pan <Jiafei.Pan@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
During the suspend process, DMA channels are suspended one by one, if one
channel cannot be suspended, all the former channels which have been suspended
should be restored, i.e. mark the pm_state as running, and release the spin
locks aquired.
This patch adds the "pm_state = RUNNING" which was omitted in the original
suspend patch.
Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
Change-Id: I924af3384d58d03f6321cb02c28a702367ea6bc1
Reviewed-on: http://git.am.freescale.net:8181/10871
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Add wake-on-lan by ARP request packets.
This feature is based on the "wake-on-filer" support.
A filer rule was added to match the incoming ARP
request packets directed to the first primary IP
address of the receiving interface.
Upon successful match during system suspend state a
FGPI interupt is triggered to wakeup the system.
Cc: Li Yang <leoli@freescale.com>
Cc: Zhao Chenhui <chenhui.zhao@freescale.com>
Change-Id: Ic00630a19a15d011ef0ee1eada660391f96018f4
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10732
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Add wake-on-lan by L2 unicast packets.
This feature is based on the "wake-on-filer" support.
A filer rule was added to match the incoming UCAST
packets during system suspend state and to trigger
the FGPI interupt to wakeup the system.
Cc: Li Yang <leoli@freescale.com>
Cc: Zhao Chenhui <chenhui.zhao@freescale.com>
Change-Id: I04d4b4a9501ea2d8f75b3e0794c220ac95b0d679
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10731
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
This framework enables eTSEC's filer and the FGPI Rx
interrupt (Filer General Purpose Interrupt) as a wakeup
source event.
Upon entering suspend state, the eTSEC filer can be
programmed with various match rules for the Rx packets.
For example, the rules could be matching incoming unicast
or arp packets. If a packet matches one of the rules, it
will be enqueued in the Rx ring and a FGPI interrupt will
be generated by the filer to wakeup the system. The packet
types not matching the rules will be dropped.
The rules need to be added as filer scripts inside
gfar_filer_config_wol() to implement different WOL
capabilities.
The "fsl,wake-on-filer" DT binding limits this
capability to certain platforms only.
Cc: Li Yang <leoli@freescale.com>
Cc: Zhao Chenhui <chenhui.zhao@freescale.com>
Change-Id: Ida38d2210975a8523e4da4fc4667de4380c2b9d4
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10730
Reviewed-by: Yang Li <LeoLi@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Not all the eTSECs have an active clock by default
when the devices enter suspend state (i.e. sleep
power state). This property is however configurable,
and all the eTSECs with wake-on-lan capabilities
can be enabled as wakeup event sources.
Use the PMC API to enable all the eTSEC ports, which
are capable of wake-on-lan, as wakeup event sources.
Cc: Li Yang <leoli@freescale.com>
Cc: Zhao Chenhui <chenhui.zhao@freescale.com>
Change-Id: I7bd3db14173ddbe3cdd64bcffeb6c72adfcbf2c7
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10729
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Don't detach the interfaces that are already down.
Use correct sequence to stop Tx traffic and
to prevent Tx timeout, including napi disabling.
Use netif_tx_lock() to prevent races while stopping
Tx, replacing the driver specific lock_tx_qs() which
is not correct for this purpose.
Use gfar_halt() to correctly stop the traffic at
controller level (i.e. graceful stop the DMA).
Fix the invalid device references for the wakeup
routines, from the invalid &dev->dev references to
the correct &ofdev->dev (or priv->dev) references.
Remove buggy device_set_wakeup_enable() from the
open() routine. Only the ethtool is allowed
to enable/disable the wol capabilities.
Remove superfluous priv->bflock lock, as it's not
justified.
Use IRQF_NO_SUSPEND to be able to wake up the system
by magic packet generated interrupts.
Change-Id: If9b4a878aa3ee6df8867bab9ca19d96b731e9fa9
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10728
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Magic Packet raises normal Fman interrupt so unmask it when
the system enters sleep/deep sleep mode such that the system
can be woken up.
Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Change-Id: I6325493dad3d0ea54a34575d6a24229fd351fbde
Reviewed-on: http://git.am.freescale.net:8181/10888
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
(cherry picked from commit a55ee50a7e6907561f21015ba8dc6a022b46722e)
Reviewed-on: http://git.am.freescale.net:8181/10924
|
|
Serge Hallyn <serge.hallyn@ubuntu.com> writes:
> Hi Oleg,
>
> commit 40a0d32d1eaffe6aac7324ca92604b6b3977eb0e :
> "fork: unify and tighten up CLONE_NEWUSER/CLONE_NEWPID checks"
> breaks lxc-attach in 3.12. That code forks a child which does
> setns() and then does a clone(CLONE_PARENT). That way the
> grandchild can be in the right namespaces (which the child was
> not) and be a child of the original task, which is the monitor.
>
> lxc-attach in 3.11 was working fine with no side effects that I
> could see. Is there a real danger in allowing CLONE_PARENT
> when current->nsproxy->pidns_for_children is not our pidns,
> or was this done out of an "over-abundance of caution"? Can we
> safely revert that new extra check?
The two fundamental things I know we can not allow are:
- A shared signal queue aka CLONE_THREAD. Because we compute the pid
and uid of the signal when we place it in the queue.
- Changing the pid and by extention pid_namespace of an existing
process.
From a parents perspective there is nothing special about the pid
namespace, to deny CLONE_PARENT, because the parent simply won't know or
care.
From the childs perspective all that is special really are shared signal
queues.
User mode threading with CLONE_PARENT|CLONE_VM|CLONE_SIGHAND and tasks
in different pid namespaces is almost certainly going to break because
it is complicated. But shared signal handlers can look at per thread
information to know which pid namespace a process is in, so I don't know
of any reason not to support CLONE_PARENT|CLONE_VM|CLONE_SIGHAND threads
at the kernel level. It would be absolutely stupid to implement but
that is a different thing.
So hmm.
Because it can do no harm, and because it is a regression let's remove
the CLONE_PARENT check and send it stable.
Change-Id: Idf491465e6d2755cd18086f49c475d36dae6570a
Cc: stable@vger.kernel.org
Acked-by: Oleg Nesterov <oleg@redhat.com>
Acked-by: Andy Lutomirski <luto@amacapital.net>
Acked-by: Serge E. Hallyn <serge.hallyn@ubuntu.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
(cherry picked from commit 1f7f4dde5c945f41a7abc2285be43d918029ecc5)
Acked-by: Bogdan Purcareata <bogdan.purcareata@freescale.com>
Change-Id: Idf491465e6d2755cd18086f49c475d36dae6570a
Reviewed-on: http://git.am.freescale.net:8181/10797
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mihai Claudiu Caraman <mihai.caraman@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
This enables certain investigation facilities when
the system is stuck. The option is present for P4 boards
(corenet32_smp_defconfig) and T4 boards
(85xx/e6500rev2_defconfig).
In particular, LXC containers use it by default.
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@freescale.com>
Change-Id: Ia761fb981ba040ed8e9b00c68ad94e95b2790189
Reviewed-on: http://git.am.freescale.net:8181/10456
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mihai Claudiu Caraman <mihai.caraman@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
This enables certain investigation facilities when
the system is stuck. The option is present for P4 boards
(corenet32_smp_defconfig) and T4 boards
(85xx/e6500rev2_defconfig).
In particular, LXC containers use it by default.
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@freescale.com>
Change-Id: I7aadd49f1966a2ef8055baad7c874798323de4ca
Reviewed-on: http://git.am.freescale.net:8181/10455
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mihai Claudiu Caraman <mihai.caraman@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
The updated DMA dts files added a new compatible "fsl,elo3-dma"
for some new platforms, and removed the property "cell-index".
So the code should be updated based on those changes.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Change-Id: I66603f76ca0feeb689c49b9eeb9c0621eb5c3897
Reviewed-on: http://git.am.freescale.net:8181/6555
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Tiefei Zang <roy.zang@freescale.com>
Reviewed-by: Thomas Trefny <Tom.Trefny@freescale.com>
(cherry picked from commit 18af7f2d2fe1f182b7c2716eaabb613d5523d2d8)
Reviewed-on: http://git.am.freescale.net:8181/10811
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Use device flag IFF_LIVE_ADDR_CHANGE to signal that
the device supports changing the hardware address when
the device is running.
This allows eth_mac_addr() to change the mac address
also when the network device's interface is open.
This capability is required by certain applications,
like bonding mode 6 (Adaptive Load Balancing).
Change-Id: Ifec3730ad8a23f656dcbeafacff786d7c1b038a4
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/1238
Reviewed-by: Xie Jianhua-B29408 <jianhua.xie@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10808
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jianhua Xie <jianhua.xie@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
This patch adds suspend resume functions for Freescale DMA driver.
.prepare callback is used to stop further descriptors from being added into the
pending queue, and also issue pending queues into execution if there is any.
.suspend callback makes sure all the pending jobs are cleaned up and all the
channels are idle, and save the mode registers.
.resume callback re-initializes the channels by restore the mode registers.
Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
Change-Id: I89826288b8d0589e42063e24c4eeeafb82b6100b
Reviewed-on: http://git.am.freescale.net:8181/10795
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Change the pme error interrupt handler to be per-CPU to avoid a warning
("Cannot set affinity for irq") when entering suspend-to-ram state.
Added IRQF_PERCPU flag.
While sending frames to the PME device, this device can return a serious error.
Added logic to properly handle this scenario. If this happens while reading
the pme database, upon resume the resulting database will not be restored.
The size of the confidence table was incorrect for a specific version of pme.
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Change-Id: Ic8cbc048c7a0e4cd8389298267ec9b4876055568
Reviewed-on: http://git.am.freescale.net:8181/9267
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
(cherry picked from commit f13d881f9e464079b62dba71f96dd73be4ad83a0)
Reviewed-on: http://git.am.freescale.net:8181/10777
|
|
During a refactoring exercise memory allocated is only released upon device exit.
Should not be freed during power management resume.
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Change-Id: Ie2f7690de0497d6adb29e5c25cf379c3ff3e46b6
Reviewed-on: http://git.am.freescale.net:8181/6847
Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com>
Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
(cherry picked from commit e15e0b2f451cdcf3579a0c42b5583c437fa74408)
Reviewed-on: http://git.am.freescale.net:8181/10776
|
|
When power is removed from the pme device, all its internal state is lost.
The suspend() function saves all necessary state in order to later resume
the device. The resume() function "writes" back the previously saved state.
The functionality is implemented as part of the pme ctrl plane device.
The state the requires saving is CCSR registers and internal SRAM memory.
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Change-Id: I27ada84b338d7905b07dcabdb2ece2a9700a764c
Reviewed-on: http://git.am.freescale.net:8181/6831
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
(cherry picked from commit d9a11a097905fbb0aa1add75c17aae7724099564)
Reviewed-on: http://git.am.freescale.net:8181/10772
|
|
mtd.name is assigned to IFC NAND physical address. Assignment type is u32.
It is not providing correct physical address of IFC NAND.
Update assignment type to u64.
This patch is alread present on sdk-kernel-3.8 branch
http://git.am.freescale.net:8181/#/c/7535/
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Change-Id: Iaea31773bb59d8d40a0399c1d0cb6c42164a089c
Reviewed-on: http://git.am.freescale.net:8181/10575
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Recycling of skb was not working. This was due to checks in
gfar_recycle_skb is getting false which results in freeing
skb every time. There is mismatch b/w skb_size calculated and
actual skb size (skb->end - skb->head).
So this patch adds EXTRA_HEADROOM when skb_size is calculated.
CR:ENGR00306216
Signed-off-by: Alok Makhariya <B46187@freescale.com>
Change-Id: I524254ceb2a7ec757645d11922e7066d0b22b756
Reviewed-on: http://git.am.freescale.net:8181/10689
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
PAMU driver suspend and resume support.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: I00eb16aa0fe8a591399349396aaced3df1dbb33b
Reviewed-on: http://git.am.freescale.net:8181/10716
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
In order for supported SoCs to enter deepsleep the QBMan ip blocks must not
have any pending interrupt status bits set in the Portals.
Therefore, in the pm callbacks for each portal, save the isdr, and clear the isr.
On the resume side, reset the save isdr.
Also fix the buffer pool depletion notification in all bman portals.
The default value is to notify them. This is an issue for unused portals, as
the portal will have the corresponding isr bit set and will prevent deepsleep
for occuring.
The unused portals need to have their ISDR and ISR cleared in order for
the qman block to enter idle state.
Also re-added the setting of ISDR clear ISR for the qbman ccsr block.
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Change-Id: Icd908215ed10d39e3f112b939c4d6b2758a97a76
Reviewed-on: http://git.am.freescale.net:8181/10717
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com>
Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
This additional parameter (window number) is required based
on the latest update of pamu driver.
Signed-off-by: Vakul Garg <vakul@freescale.com>
Change-Id: I14a4d61c6f6790aa87ce5924bb9893d9170e8a76
Reviewed-on: http://git.am.freescale.net:8181/10719
Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Set the register IPPDEXPCR (IP Powerdown Exception Control Register) to
enable IP blocks which work as wakeup source when sleep/deep sleep.
Change-Id: Id95cb920cab90e12851995d039bd866e6388f8ae
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10711
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
"fsl,p104xrdb-cpld" -> "fsl,t104xrdb-cpld"
Change-Id: I30d83d1867022485008b48c3d7d601040b840621
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10710
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
T104x has deep sleep feature, which can switch off most parts of
the SoC when it is in deep sleep mode. This way, it becomes more
energy-efficient.
The DDR controller will also be powered off in deep sleep. Therefore,
the last stage (the latter part of fsl_dp_enter_low) will run without DDR
access. This piece of code and related TLBs are prefetched in advance.
Due to the different initialization code between 32-bit and 64-bit, they
have seperate resume entry and precedure.
The feature supports 32-bit and 64-bit kernel mode.
Change-Id: I9b9b9188fdc67167030658b6cc1d0a1cbe7e2180
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10709
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
In the last stage of deep sleep, software will trigger a Finite
State Machine (FSM) to control the hardware precedure, such as
board isolation, killing PLLs, removing power, and so on.
When the system is waked up by an interrupt, the FSM controls the
hardware to complete the early resume precedure.
This patch configure the EPU FSM preparing for deep sleep.
Change-Id: I42b196a656324260c1d1cfcf688016c6f8d7ebe8
Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10708
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
In sleep mode, the clocks of e500 cores and unused IP blocks is
turned off. The IP blocks which are allowed to wake up the processor
are still running.
The sleep mode is equal to the Standby state in Linux. Use the
command to enter sleep mode:
echo standby > /sys/power/state
Change-Id: I1cf82fddc34a9c0ad3cb66ae554e5521805365e6
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10707
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.
The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.
There are two versions of register map in RCPM, which is specified by
the compatible entry in the RCPM node of device tree.
Change-Id: I113211311c7241df95f067103d0ed81ada26d2ed
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10706
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback function will flush all caches in the current cpu.
Change-Id: Id6da30ac5490cac5f5669909df2152f0ee952086
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10705
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
In 64-bit mode, kernel just clears the irq soft-enable flag
in struct paca_struct to disable external irqs. But, in
the case of suspend, irqs should be disabled by hardware.
Therefore, use hard_irq_disable() instead of local_irq_disable().
Change-Id: I743ec4971a9e1a9b5a3c2b463324588d48af65af
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10704
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Change-Id: I30aa0bc40fcbe8d6abb2511dbf7bfb31397078e6
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10643
Reviewed-by: Nir Erez <nir.erez@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Change-Id: I26fd2c48e2dbb680e51cf5abdea5345f7e2694be
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10642
Reviewed-by: Eyal Harari <Eyal.Harari@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Multiply the number of work queues by the number of 802.1p PFC
priorities.
With this patch, egress traffic can be classiffied on different work
queues depending on the skb priority.
Each work queue can be paused by a PFC priority.
When the private interfaces' buffer pool depletes, PFC frames are
issued with all configured priorities set in the Class-Enable Vector.
Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com>
Change-Id: Ibaf928e547c662dacf08063bd94953b9cf6138e0
Reviewed-on: http://git.am.freescale.net:8181/10498
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
|
|
As PFC support is in the experimental phase, the default number of
Classes of Service is set to a minimum of 3.
Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com>
Change-Id: I5a2848788617a00cd72f2db51febcb4023a9bef5
Reviewed-on: http://git.am.freescale.net:8181/10652
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Reviewed-by: Ehud Shiff <Ehud.Shiff@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
The BMan Pool Depletion Register (FMBM_RMPD) has 8 bits for
- NBPDE - Buffer Pools Depleted Enable
- QbbPEV - 802.1Qbb Priority Enable Vector
- SBPD - Single Buffer Pool Depletion
This patch takes into account all the 8 bits for each of these fields.
Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com>
Change-Id: Ie373c6b12501b7005233095ca480fb1bdad57416
Reviewed-on: http://git.am.freescale.net:8181/10606
Reviewed-by: Ehud Shiff <Ehud.Shiff@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Change-Id: I0058a7152ec34038961bdfb7598d280b7ec47777
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10411
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Change-Id: I5614f271b89f912553e9a6558c4256c7c54ba6e8
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10410
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
|
|
This patch avoids modifying the structures defined in 'fm_ext.h' and
configures all PFC buffer pool depletion parameters in
'CheckNConfigFmPortAdvArgs', between 'FM_PORT_Config' and
'FM_PORT_Init'.
Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com>
Change-Id: I7268fa71416cb25f0cb42b56cd89a702996801fa
Reviewed-on: http://git.am.freescale.net:8181/10605
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
|
|
The SDK no longer supports rev1.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: Ief0e72d5305b16f994df3beca58134dd96e8aff7
Reviewed-on: http://git.am.freescale.net:8181/10273
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
The SDK no longer supports e6500 rev1.
This reverts commit 38043080bb90f931efbe56a3f407c18206985f18
"powerpc/e6500: extend TLB miss lock to invalidations"
and commit b9e282e1347b771b736a84e6b0a1048c551e6a6c
"powerpc/e6500: add kconfig option for erratum A-004801"
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: I749f497cbb6b96d045434065b869b253f01d6575
Reviewed-on: http://git.am.freescale.net:8181/10272
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
This reverts commit f4c0e693ccc3422c5b809e7cc8f59b7637e3b7ab.
rev1 is no longer supported in the SDK, and the workaround for A-006198
conflicts with machine check support.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: I64e1ce19eb59a6bba8649156597cc49ff9b62b1e
Reviewed-on: http://git.am.freescale.net:8181/10271
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Add device-id entry for N25Q512A in device_id structure.
Flash has following features:
-64MB size, 1.8V, Mulitple I/O, 4KB Sector erase memory.
-Memory is organised as 1024(64KB) main sectors.
-Each sector is divided into 256 pages.
-Register set/Opcodes are similar to other N25Q family products
-Device ID: 20ba20
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Change-Id: Ifd191e1f2b0fb94ad7f37ff08dbf60f8e1617991
Reviewed-on: http://git.am.freescale.net:8181/10594
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
| drivers/uio/fsl_sec_uio.c: In function 'fsl_sec_jr_probe':
| drivers/uio/fsl_sec_uio.c:186:2: error: implicit declaration of function 'of_address_to_resource' [-Werror=implicit-function-declaration]
| ret = of_address_to_resource(jr_node, 0, ®s);
| ^
| drivers/uio/fsl_sec_uio.c:211:2: error: implicit declaration of function 'irq_of_parse_and_map' [-Werror=implicit-function-declaration]
| jr->irq = irq_of_parse_and_map(jr_node, 0);
| ^
| drivers/uio/fsl_sec_uio.c: In function 'fsl_sec_probe':
| drivers/uio/fsl_sec_uio.c:296:2: error: implicit declaration of function 'of_iomap' [-Werror=implicit-function-declaration]
| sec_dev->global_regs = of_iomap(sec_node, 0);
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Change-Id: I5bcaa4e15c48c7aa80edb478ac86ad1aa6f2eea4
Reviewed-on: http://git.am.freescale.net:8181/10591
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Once the PCIe device assigned to a guest VM (via VFIO) gets detached from the iommu domain
(when guest terminates), its PAMU table entry is disabled. So, this would prevent the device
from being used once it's assigned back to the host.
This patch allows for creation of a default DMA window corresponding to the device
and subsequently enabling the PAMU table entry. Before we enable the entry, we ensure that
the device's bus master capability is disabled (device quiesced).
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: Iab4da4adfac8536a6834011431a395ba3a4982d2
Reviewed-on: http://git.am.freescale.net:8181/10257
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
Factor out PCI specific code in the PAMU driver.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: Ia6d73dca46b7274e14f7d7099aaef22d6510d1aa
Reviewed-on: http://git.am.freescale.net:8181/10256
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
If a process explictly unmapped DMA fragments the reference
count of each fragement wasn't properly decremented causing
a leak. This would only occur if the proccess explicitly
umapped the memory, exiting the process did correctly adjust
the reference counts
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Change-Id: Ia9adfccd5249d17d5506796b1fe71c32f46cab30
Reviewed-on: http://git.am.freescale.net:8181/10527
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
asf_gianfar will compile only when CONFIG_GIANFAR
and CONFIG_AS_FASTPATH are set.
Replacing CONFIG_RX_TX_BUFF_XCHG with CONFIG_AS_FASTPATH
and CONFIG_GIANFAR in skbuff structure of skbuff.h
Removing CONFIG_RX_TX_BUFF_XCHG flag from kconfig.
Change-Id: Iba0da980dfb807808cb3f9cd7d18a0229fa96b35
CR:ENGR00306399
Signed-off-by: Alok Makhariya <B46187@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10535
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
So far the DIU driver does not have a mechanism to do the
board specific initialization. So on some platforms,
such as P1022, 8610 and 5121, The board specific initialization
is implmented in the platform file such p10222_ds.
Actually, the DIU is already intialized in the u-boot, the pin sharing
and the signal routing are also set in u-boot. So we can leverage that
in kernel driver to avoid board sepecific initialization, especially
for the corenet platform, which is the abstraction for serveral
platfroms.
The potential problem is that when the system wakeup from the deep
sleep, some platform settings may need to be re-initialized. The CPLD
and FPGA settings will be kept, but the pixel clock register which
usually locate at the global utility space need to be reinitialized.
Generally, the pixel clock setting was implemented in the platform
file, But the pixel clock register itself should be part of the DIU
module, And for P1022,8610 and T1040, the pixel clock register have the
same structure, So we can consider to move the pixel clock setting
from the platform to the diu driver. This patch provide the options
set the pixel clock in the diu driver. But the original platform pixel
clock setting stil can be used for P1022,8610 and 512x without any
update. To implement the pixel clock setting in the diu driver. the
following update in the diu dts node was needed.
display:display@180000 {
compatible = "fsl,t1040-diu", "fsl,diu";
- reg = <0x180000 1000>;
+ reg = <0x180000 1000 0xfc028 4>;
pixclk = <0 255 0>;
interrupts = <74 2 0 0>;
}
The 0xfc028 is the offset for pixel clock register. the 3 segment of
the pixclk stand for the PXCKDLYDIR, the max of PXCK and the
PXCKDLY which will be used by the pixel clock register setting.
This was tested on T1040 platform. For other platform, the original
node together with the platform settings still can work.
The binding update also included in this patch.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Change-Id: I0663914b08378fc7852eab788801f4e5dc59977d
Reviewed-on: http://git.am.freescale.net:8181/10327
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
|
This driver config the L2 Cache to be SRAM mode and map the SRAM to user
space. The size and the address of SRAM are passed in the U-boot command
line as format: cache-sram=addr,size.
Please notice that this driver is exclusive with config FSL_85XX_CACHE_SRAM.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Change-Id: Ib0433acd459413fec5f5218751b0db79309895fd
Reviewed-on: http://git.am.freescale.net:8181/10295
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Po Liu <Po.Liu@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
|
