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KVM need this function when switching from vcpu to user-space
thread. My subsequent patch will use this function.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
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"ehpriv" instruction is used for setting software breakpoints
by user space. This patch adds support to exit to user space
with "run->debug" have relevant information.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
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This allows the exit to user space if emulator request by returning
EMULATE_EXIT_USER. This will be used in subsequent patches in list
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
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Currently the instruction emulator code returns EMULATE_EXIT_USER
and common code initializes the "run->exit_reason = .." and
"vcpu->arch.hcall_needed = .." with one fixed reason.
But there can be different reasons when emulator need to exit
to user space. To support that the "run->exit_reason = .."
and "vcpu->arch.hcall_needed = .." initialization is moved a
level up to emulator.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
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Instruction emulation return EMULATE_DO_PAPR when it requires
exit to userspace on book3s. Similar return is required
for booke. EMULATE_DO_PAPR reads out to be confusing so it is
renamed to EMULATE_EXIT_USER.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
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This patch defines the interface parameter for KVM_SET_GUEST_DEBUG
ioctl support. Follow up patches will use this for setting up
hardware breakpoints, watchpoints and software breakpoints.
Also kvm_arch_vcpu_ioctl_set_guest_debug() is brought one level below.
This is because I am not sure what is required for book3s. So this ioctl
behaviour will not change for book3s.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
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For using the rapidio message and doorbell units in linux user space,
need to build the uio devices in kernel space. The message and
doorbell uio devices in kernel will map the units registers to user
space and then the applications in user space can configure those
registers and use the rapidio message and doorbell units.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Change-Id: Icfbc6e3cedc627b88143ae1656e6aebc4bd75684
Reviewed-on: http://git.am.freescale.net:8181/981
Reviewed-by: Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
Reviewed-by: Zang Tiefei-R61911 <tie-fei.zang@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Add support to expose FSL PPC DMA controller to user space. Each DMA
controller is split until multiple (normally four) separate channels.
We map each channel into a unique UIO device.
Signed-off-by: Kai Jiang <Kai.Jiang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Change-Id: I6914bda4bf59ccf6a9f261b88260f03e7965ffa3
Reviewed-on: http://git.am.freescale.net:8181/980
Reviewed-by: Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
Reviewed-by: Zang Tiefei-R61911 <tie-fei.zang@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Add support to expose Serial RapidIO controller to user space. We
split the controller between general control and per port memory bus
access.
Also add support to handle the SRIO error interrupt.
Signed-off-by: Kai Jiang <Kai.Jiang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Change-Id: Ic8ef32d5b665a94b35a3dd174691c3eca41339ea
Reviewed-on: http://git.am.freescale.net:8181/979
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Emulate TMCFG0 TMRN register exposing one HW thread per vcpu.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Change-Id: I979a199c089a01d4f8039496314ae44512f9b980
Reviewed-on: http://git.am.freescale.net:8181/1474
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Emulate MCSRR0/1 SPR and rfmci instruction since they are used by A-006198
erratum fix.
Also fix kvm_exit_names array in the process.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Change-Id: I15372519a9b3010ab8dfb43255a8b78ef10c4893
Reviewed-on: http://git.am.freescale.net:8181/1299
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Add e6500 core to Kconfig description.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Change-Id: I6b073aec408739315df9573e10271541e2f9f4d1
Reviewed-on: http://git.am.freescale.net:8181/1255
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Extend processor compatibility names to e6500 cores.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Change-Id: Ibbf4e2e3d65c4192fe92dc75efb32e6f870fe2bd
Reviewed-on: http://git.am.freescale.net:8181/1254
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Embedded.Page Table (E.PT) category is not supported yet in e6500 kernel.
Configure TLBnCFG to remove E.PT and E.HV.LRAT categories from VCPUs.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Change-Id: Id2d73fd09784f9bfb741f1126b6772d841303e7e
Reviewed-on: http://git.am.freescale.net:8181/1253
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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MMU registers were exposed to user-space using sregs interface. Add them
to ONE_REG interface using kvmppc_get_one_reg/kvmppc_set_one_reg delegation
mechanism.
Add support for TLBnPS registers available in MMU Architecture Version
(MAV) 2.0.
EPTCFG register defined by E.PT is accessed unconditionally by Linux guests
in the presence of MAV 2.0. Emulate it now.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Change-Id: Idb1a31de66d9c649ac303631032edb7c8aefbb8f
Reviewed-on: http://git.am.freescale.net:8181/1252
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Vcpu's MMU default configuration and geometry update logic was buried in
a chunk of code. Move them to dedicated functions to add more clarity.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Change-Id: Ia352aaa01b3a2c981408525a3a3c09a016fee1e2
Reviewed-on: http://git.am.freescale.net:8181/1251
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Refactor Book3E ONE_REG ioctl implementation to use kvmppc_get_one_reg/
kvmppc_set_one_reg delegation interface introduced by Book3S. This is
necessary for MMU SPRs which are platform specifics.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Change-Id: Iac2d6108f6fc0798a54d3c8f2bf0e33d51057b55
Reviewed-on: http://git.am.freescale.net:8181/1249
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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We can not leave those parameters un-initialized, otherwise, kernel boot up may
pick random values for those two parameters then crash at:
"
fsl_dpa: dpaa_eth.c:4217:dpa_load() fsl_dpa: FSL DPAA Ethernet driver ()
cpu0: ! MAJOR FM-SP Error [CPU00, drivers/net/ethernet/freescale/fman/
Peripherals/FM/SP/fm_sp.c:403 FmSpCheckBufMargins]: Invalid Value;
"
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I86aabcaf7a895b020456e3a01aff19425b03a17d
Reviewed-on: http://git.am.freescale.net:8181/1404
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Change the data type of several fields used in network interface statistics.
'dpa_get_stats64' replaces 'dpa_get_stats' and 'u64' replaces 'u32'.
Use a new function for calculating statistics. 'dpa_get_stats64' replaces
'dpa_get_stats'.
Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com>
Change-Id: I580a531315067b73692ec2a21e0f78552c8da381
Reviewed-on: http://git.am.freescale.net:8181/1401
Reviewed-by: Radulescu Ruxandra Ioana-B05472 <ruxandra.radulescu@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Switch the default compile option from "optimize for ipfwd" to "optimize
for termination".
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Change-Id: I37b9b867b2f9787eb4a56a8005e198a2fb6430cc
Reviewed-on: http://git.am.freescale.net:8181/1400
Reviewed-by: Radulescu Ruxandra Ioana-B05472 <ruxandra.radulescu@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Kernel 3.8 brings a new way of organizing the netdev features
(feature sets include hardware features, currently enabled features,
vlan features and wanted features). Some ethtool ops also replaced
by a set of new ndo's.
Update the DPAA Ethernet driver to account for these changes.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Change-Id: I073920040f9c92665773cac5fb30d305320699be
Reviewed-on: http://git.am.freescale.net:8181/1399
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Signed-off-by: Sachin Saxena <sachin.saxena@freescale.com>
CQ ID : ENGR00253307
Change-Id: I7441da8faab12440b51604e6c1d00bccc17a37e5
Reviewed-on: http://git.am.freescale.net:8181/1347
Reviewed-by: Gupta Rajan-B15745 <rajan.gupta@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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- Support added to offload both Rules via iptables &ip6tables tool
- Only MANGLE table supported with POSTROUTING Hook.
Signed-off-by: Sachin Saxena <sachin.saxena@freescale.com>
CQ ID : ENGR00253307
Change-Id: I4df4245091ef0e195e058dce4fb611b04746061c
Reviewed-on: http://git.am.freescale.net:8181/1346
Reviewed-by: Gupta Rajan-B15745 <rajan.gupta@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Signed-off-by: Sachin Saxena <sachin.saxena@freescale.com>
CQ ID : ENGR00253307
Change-Id: If090285cc4fdfe6a09bd62da1697a55404cdbce4
Reviewed-on: http://git.am.freescale.net:8181/1345
Reviewed-by: Gupta Rajan-B15745 <rajan.gupta@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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eMMC build-in in T4 board can't work when use ADMA transfer data,
but for SDHC card it work well. No ERRATA and relevant bugfix
for this issue, so use SDMA instead get it working fist.
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Change-Id: Ifdb8cf3caa7b1904c252e435e94254d089ec23c4
Reviewed-on: http://git.am.freescale.net:8181/1215
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: Ie84e3f6f73d85ca07745bb4b1df2d90e6a31a021
Reviewed-on: http://git.am.freescale.net:8181/1356
Reviewed-by: Aggrwal Poonam-B10812 <Poonam.Aggrwal@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor
state can execute TLB management instructions. If EPCR[DGTMI]=0
tlbwe and tlbilx are allowed to execute normally in the guest state.
A hypervisor may choose to virtualize TLB1 and for this purpose it
may use IPROT to protect the entries for being invalidated by the
guest. However, because tlbwe and tlbilx execution in the guest state
are sharing the same bit, it is not possible to have a scenario where
tlbwe is allowed to be executed in guest state and tlbilx traps. When
guest TLB management instructions are allowed to be executed in guest
state the guest cannot use tlbilx to invalidate TLB1 guest entries.
Linux is using tlbilx in the boot code to invalidate the temporary
entries it creates when initializing the MMU. The patch is replacing
the usage of tlbilx in initialization code with tlbwe with VALID bit
cleared.
Linux is also using tlbilx in other contexts (like huge pages or
indirect entries) but removing the tlbilx from the initialization code
offers the possibility to have scenarios under hypervisor which are
not using huge pages or indirect entries.
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Iebc083d54b16582bdb3a77fbddde75c1fc61f741
Reviewed-on: http://git.am.freescale.net:8181/1236
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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corenet64_smp_defconfig
Otherwise there wil be no SCSI device nodes.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Change-Id: I86f9531d9b88d0fabfba4b1dcfd3f9e20bdcd576
Reviewed-on: http://git.am.freescale.net:8181/1392
Reviewed-by: Zang Tiefei-R61911 <tie-fei.zang@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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BSC913x are heterogeneous platforms having DSP and PowerPC.
* Lot of new IPs like AIC (Antenna Interface Controller), RF (radio) etc
* Such IPs are not present in any other 85xx platform
* Lot of optimizations related to ethernet/ASF (Application Specific Fastpath)
are enabled in this config
For 913x platforms having more than one core, bsc913x_smp_defconfig is also
added. Beyond CONFIG_SMP=y and its dependencies,this should be identical
to bsc913x_defconfig
Signed-off-by: Harninder Rai <harninder.rai@freescale.com>
Change-Id: I2266e57c2136f85d08d64835959755bbce110301
Reviewed-on: http://git.am.freescale.net:8181/924
Reviewed-by: Gala Kumar-B11780 <kumar.gala@freescale.com>
Reviewed-by: Burmi Naveen-B16502 <NaveenBurmi@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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commit be7eb995
dpaa_eth: Update PR processing routine on Rx path
leaves an unitialized variable which triggers a compiler warning.
Eliminating the unnecessary declaration.
To avoid resubmitting the whole set of patches after that one, I'm
adding this fix.
*** Please squash this with "commit be7eb995
*** dpaa_eth: Update PR processing routine on Rx path" ***
Change-Id: Id9d99a2b9ec53d87560d5367a22c1f1c67aa5b39
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/1289
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Eliminate a couple of #warning directives that are no longer useful.
Change-Id: Ifafe15f50a7eaa031f0b0a87a8655ccf1ee4b1e7
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/1283
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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The "lockless tx" capability, although flagged as deprecated, was deemed
closer to upstreamability than our previous NETIF_F_HW_QDISC (meanwhile
moved under ASF config). This has shown no performance impact
whatsoever, at least in termination/netperf tests.
Change-Id: I0294f0f105e56cc00cb957c23a3a6c6d3acc8d6f
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/1282
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Due to opposition from the kernel netdevs, unstaging the Hw Qdisc as a
standard capability and moving it to ASF instead.
Change-Id: I79592b273eac12650d6dab1662a5901725a9c5a9
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/1281
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Do not limit IP Reassembled frames to MTU size.
Change-Id: I8ec3ca5e23165d7ee6397935dff26c7a18903fef
Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/1280
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Make several changes to the logic of the parse results processing
function on the Rx path.
Currently all frames with a parser header error are received on the
error frame queue, so the processing of PR on the default rx path
doesn't need to check for header errors.
Remove both the checks and a counter that was supposed to count
frames with an invalid L4 header.
Change-Id: Ibe7eb9957e1a0c78abf8445f758067340b48cd86
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/1279
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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The p1020rdb-pd has the similar feature as the p1020rdb.
Therefore, p1020rdb-pd use the same platform file as the p1/p2 rdb board.
Overview of P1020RDB-PD platform:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 2 USB ports
- 4 TDM ports
- PCIe
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
Change-Id: Ie5295fe5ba8b4490ab6b4c9a6fb85453da759f9a
Reviewed-on: http://git.am.freescale.net:8181/1273
Reviewed-by: Xie Xiaobo-R63061 <X.Xie@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
Change-Id: Ia9a6afd32ce096c14e55c1ba3cbd663eb24a51ff
Reviewed-on: http://git.am.freescale.net:8181/1272
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Use device flag IFF_LIVE_ADDR_CHANGE to signal that
the device supports changing the hardware address when
the device is running.
This allows eth_mac_addr() to change the mac address
also when the network device's interface is open.
This capability is required by certain applications,
like bonding mode 6 (Adaptive Load Balancing).
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: I12e5ceb3dbfe0b5a5e3e2602dc0b46815ca7b927
Reviewed-on: http://git.am.freescale.net:8181/1238
Reviewed-by: Xie Jianhua-B29408 <jianhua.xie@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Two command line parameters are combined into one since they
should always be used simultaneously.
The term offset is misleading, replace it with addr as it
represents a physical address.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: I46cb777524248c3cc9c84b6e131a5cb513a652ab
Reviewed-on: http://git.am.freescale.net:8181/1237
Reviewed-by: Tang Yuantian-B29983 <yuantian.tang@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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The QMan revision on both T4240 and B4860 rev2 silicon is 3.1, and both T2080
and T1040 also have QMan rev3.1. Update the qman driver to support rev3.1.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I7ea2149f982023cd5f99729df6c6b61cba46b668
Reviewed-on: http://git.am.freescale.net:8181/1261
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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- Fix the parameter order in disable ceetm mode of sp.
- Alloc memory for CQ after confirming CQ is available for group CQs
- Check prio_b to be non-zero if group_b is set.
- Use object qm_ceetm_weight_code to convert wbfs and ratio.
- Adjust weight code index from W8 to W15 in set/get queue weight
- Fix the byte_cnt field of ceetm statistics counter
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I28e4978e1cc13957e64dd6f0e376d239d1161933
Reviewed-on: http://git.am.freescale.net:8181/1260
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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The CEETM congestion state change notification uses a seperate bit for CSCN
interrupt in software portal's ISR register, and different command to query
congestion state. This patch implmentes the CCSCI interrupt handling, and
combines the ccg's swp setting into qman_ceetm_ccg_set(), because we can only
register ccgr callback to the affine portal.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I246bd70ea33786d39b6a18ae90e03f9fa09c3912
Reviewed-on: http://git.am.freescale.net:8181/1259
Reviewed-by: Thorpe Geoff-R01361 <Geoff.Thorpe@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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CGR objects registered against a portal can receive CSCN notifications
via that portal, and this supports the existence of there being more than
one CGR object for the same CGRID (eg. two distinct drivers using the
same portal and using FQs that are subscribed to the same CGR). The
portal code was previously using a distinct list of registered CGRs for
every possible CGRID, ie. a 256-element array of lists! This meant that
when CSCN interrupts occurred and a 256-bit mask was calculated
indicating which CGRIDs had changed state, we would iterate that bitmask
and for each CGRID that had changed, we would iterate the corresponding
list from the array, invoking callbacks for all CGR objects.
Now, we just use a singe list for all CGRs, irrespective of CGRID. Rather
than iterating the bitmask by CGRID and, for each CGRID that had a
state-change, iterating the corresponding CGR list to invoke callbacks,
we now just iterate the single CGR list and for each CGR with a callback,
we check the bit in the bitmask corresponding to the CGRID to determine
whether to invoke the callback.
This is a more efficient use of memory (the 256-element array of lists
used 2KB per portal on 32-bit cores, 4KB on 64-bit), and the code becomes
simpler. And the "downside" doesn't occur, because there are never more
than a small handful of CGR objects per portal at most, and quite often
only one or two (or even none). So a single list is probably as efficient
or even better in the conventional use cases, and much less wasteful of
space.
Furthermore, this logic will be extended for CEETM CCGRs, of which there
are many more than for regular CGRs. So without this change, the
extensions for CEETM would continue the previous bad approach, but with 2
or 4 times the unwelcome footprint.
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Change-Id: I00ff60edf191aabc9105c0b49e7437fad085f7dc
Reviewed-on: http://git.am.freescale.net:8181/1258
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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The dpaa 1588 can be disabled/enabled via sysfs in runtime.
By default, the dpaa 1588 is disabled, that means no 1588
action activated during the processing of ethernet frames.
To enable 1588:
echo 1 > /sys/devices/<DIR>/fmx-gby/ptp_1588
To disable 1588:
echo 0 > /sys/devices/<DIR>/fmx-gby/ptp_1588
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: I9f21f47c1f5eeb7b5f05e43e2ec6fe41fa3e697f
Reviewed-on: http://git.am.freescale.net:8181/1150
Reviewed-by: Hamciuc Bogdan-BHAMCIU1 <bogdan.hamciuc@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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In case of overloading the slaves, the performace will get worse
since there are more and more outdated timestamps accumulated in
Tx buffer, so we introduce a way to remove those older timestamps
between the current matched one and the tail if they are more than
TS_ACCUMULATION_THRESHOLD. In addition, we update the buffer size
to 256 which is enough according to stress tests.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: I761dcabf71f27d47627ca835daf28562bfa37319
Reviewed-on: http://git.am.freescale.net:8181/1146
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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On mfspr/mtspr emulation path Book3E's MMUCFG SPR with value 1015 clashes
with G4's MSSSR0 SPR. Move MSSSR0 emulation from generic part to Books3S.
MSSSR0 also clashes with Book3S's DABRX SPR. DABRX was not explicitly
handled so Book3S execution flow will behave as before.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Change-Id: Ie4530a47a3b9a1121a74fc3314ac35255cc0591e
Reviewed-on: http://git.am.freescale.net:8181/1250
Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Exporting gfar_new_skb() for allocating new SKBs required
for transmitting fragmented packets in offload engine like ASF.
Change-Id: Ic7b3ad625c3132e5ed4d77d67d67f434c1ddaf05
Signed-off-by: Rajan Gupta <rajan.gupta@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/1337
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Change-Id: I3f7ba9fd42e0aa320bc59ecd5062d0e46f77c21c
Signed-off-by: Rajan Gupta <rajan.gupta@freescale.com>
Signed-off-by: Sachin Saxena <sachin.saxena@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/1336
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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Add a separate NAPI poll routine for Tx cleanup to be triggerred independently
by the Tx confirmation interrupts only. Existing poll function is modified to
handle only the Rx path processing. The Tx poll routine does not need a budget,
since Tx processing doesn't consume NAPI budget, and hence it is registered
with minimum NAPI weight. This way the Tx poll routine won't compete for budget
with the Rx poll routine. The Rx poll routine is registered with the maximum
NAPI weight, just as before.
The gfar_configure_coalescing function is simply split in two so that the
coalescing timers can be updated separately between the Rx and Tx paths.
The schedule cleanup ISR part has been changed to handle the Rx and Tx
interrupts independently (since we have separate interrupt lines for Rx and Tx).
NAPI scheduling does not require locking since we have different NAPI instances
between the Rx and Tx confirmation paths now.
This generaly improves the driver's response, most notably when forwading
multiple opposite flows.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: I21fee0f7853f46dead0d02ff39cce60c20e624db
Reviewed-on: http://git.am.freescale.net:8181/1165
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
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