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2014-04-07fsl_qbman: Add support for deepsleepJeffrey Ladouceur
In order for supported SoCs to enter deepsleep the QBMan ip blocks must not have any pending interrupt status bits set in the Portals. Therefore, in the pm callbacks for each portal, save the isdr, and clear the isr. On the resume side, reset the save isdr. Also fix the buffer pool depletion notification in all bman portals. The default value is to notify them. This is an issue for unused portals, as the portal will have the corresponding isr bit set and will prevent deepsleep for occuring. The unused portals need to have their ISDR and ISR cleared in order for the qman block to enter idle state. Also re-added the setting of ISDR clear ISR for the qbman ccsr block. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Change-Id: Icd908215ed10d39e3f112b939c4d6b2758a97a76 Reviewed-on: http://git.am.freescale.net:8181/10717 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com> Reviewed-by: Roy Pledge <roy.pledge@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-07fsl_qbman: set stash attr window before setting attributeVakul Garg
This additional parameter (window number) is required based on the latest update of pamu driver. Signed-off-by: Vakul Garg <vakul@freescale.com> Change-Id: I14a4d61c6f6790aa87ce5924bb9893d9170e8a76 Reviewed-on: http://git.am.freescale.net:8181/10719 Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-05powerpc/t104x: enable wakeup sourcesChenhui Zhao
Set the register IPPDEXPCR (IP Powerdown Exception Control Register) to enable IP blocks which work as wakeup source when sleep/deep sleep. Change-Id: Id95cb920cab90e12851995d039bd866e6388f8ae Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10711 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-05powerpc/t104x: fix typoChenhui Zhao
"fsl,p104xrdb-cpld" -> "fsl,t104xrdb-cpld" Change-Id: I30d83d1867022485008b48c3d7d601040b840621 Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10710 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-05powerpc/pm: support deep sleep feature on T104xChenhui Zhao
T104x has deep sleep feature, which can switch off most parts of the SoC when it is in deep sleep mode. This way, it becomes more energy-efficient. The DDR controller will also be powered off in deep sleep. Therefore, the last stage (the latter part of fsl_dp_enter_low) will run without DDR access. This piece of code and related TLBs are prefetched in advance. Due to the different initialization code between 32-bit and 64-bit, they have seperate resume entry and precedure. The feature supports 32-bit and 64-bit kernel mode. Change-Id: I9b9b9188fdc67167030658b6cc1d0a1cbe7e2180 Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10709 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-05drivers/fsl: add EPU FSM configuration for deep sleepChenhui Zhao
In the last stage of deep sleep, software will trigger a Finite State Machine (FSM) to control the hardware precedure, such as board isolation, killing PLLs, removing power, and so on. When the system is waked up by an interrupt, the FSM controls the hardware to complete the early resume precedure. This patch configure the EPU FSM preparing for deep sleep. Change-Id: I42b196a656324260c1d1cfcf688016c6f8d7ebe8 Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10708 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-05powerpc/85xx: support sleep feature on QorIQ SoCs with RCPMChenhui Zhao
In sleep mode, the clocks of e500 cores and unused IP blocks is turned off. The IP blocks which are allowed to wake up the processor are still running. The sleep mode is equal to the Standby state in Linux. Use the command to enter sleep mode: echo standby > /sys/power/state Change-Id: I1cf82fddc34a9c0ad3cb66ae554e5521805365e6 Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10707 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-05powerpc/rcpm: add RCPM driverChenhui Zhao
There is a RCPM (Run Control/Power Management) in Freescale QorIQ series processors. The device performs tasks associated with device run control and power management. The driver implements some features: mask/unmask irq, enter/exit low power states, freeze time base, etc. There are two versions of register map in RCPM, which is specified by the compatible entry in the RCPM node of device tree. Change-Id: I113211311c7241df95f067103d0ed81ada26d2ed Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10706 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-04powerpc/cache: add cache flush operation for various e500Chenhui Zhao
Various e500 core have different cache architecture, so they need different cache flush operations. Therefore, add a callback function cpu_flush_caches to the struct cpu_spec. The cache flush operation for the specific kind of e500 is selected at init time. The callback function will flush all caches in the current cpu. Change-Id: Id6da30ac5490cac5f5669909df2152f0ee952086 Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10705 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-04powerpc/suspend: disable irq by hardware when suspendChenhui Zhao
In 64-bit mode, kernel just clears the irq soft-enable flag in struct paca_struct to disable external irqs. But, in the case of suspend, irqs should be disabled by hardware. Therefore, use hard_irq_disable() instead of local_irq_disable(). Change-Id: I743ec4971a9e1a9b5a3c2b463324588d48af65af Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10704 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-04fmd: adjust MURAM size to fit B4rev2.xMandy Lavi
Change-Id: I30aa0bc40fcbe8d6abb2511dbf7bfb31397078e6 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10643 Reviewed-by: Nir Erez <nir.erez@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-04fmd: fix warning prt-to-uintMandy Lavi
Change-Id: I26fd2c48e2dbb680e51cf5abdea5345f7e2694be Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10642 Reviewed-by: Eyal Harari <Eyal.Harari@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-04dpaa: add PFC supportCristian Bercaru
Multiply the number of work queues by the number of 802.1p PFC priorities. With this patch, egress traffic can be classiffied on different work queues depending on the skb priority. Each work queue can be paused by a PFC priority. When the private interfaces' buffer pool depletes, PFC frames are issued with all configured priorities set in the Class-Enable Vector. Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com> Change-Id: Ibaf928e547c662dacf08063bd94953b9cf6138e0 Reviewed-on: http://git.am.freescale.net:8181/10498 Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com> Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
2014-04-04FMD: set the default number of PFC Classes of Service to a minimum of 3Cristian Bercaru
As PFC support is in the experimental phase, the default number of Classes of Service is set to a minimum of 3. Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com> Change-Id: I5a2848788617a00cd72f2db51febcb4023a9bef5 Reviewed-on: http://git.am.freescale.net:8181/10652 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com> Reviewed-by: Ehud Shiff <Ehud.Shiff@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-04FMD: enable multiple priorities per PFC frameCristian Bercaru
The BMan Pool Depletion Register (FMBM_RMPD) has 8 bits for - NBPDE - Buffer Pools Depleted Enable - QbbPEV - 802.1Qbb Priority Enable Vector - SBPD - Single Buffer Pool Depletion This patch takes into account all the 8 bits for each of these fields. Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com> Change-Id: Ie373c6b12501b7005233095ca480fb1bdad57416 Reviewed-on: http://git.am.freescale.net:8181/10606 Reviewed-by: Ehud Shiff <Ehud.Shiff@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-03fmd: Handled clearing of plcr profile and scheme for re-useMandy Lavi
Change-Id: I0058a7152ec34038961bdfb7598d280b7ec47777 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10411 Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-03fmd: kg: add support for independent extractions of IPv6 TC+VER and FLMandy Lavi
Change-Id: I5614f271b89f912553e9a6558c4256c7c54ba6e8 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10410 Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-03FMD: remove unnecessary buffer pool depletion parametersCristian Bercaru
This patch avoids modifying the structures defined in 'fm_ext.h' and configures all PFC buffer pool depletion parameters in 'CheckNConfigFmPortAdvArgs', between 'FM_PORT_Config' and 'FM_PORT_Init'. Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com> Change-Id: I7268fa71416cb25f0cb42b56cd89a702996801fa Reviewed-on: http://git.am.freescale.net:8181/10605 Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com> Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com> Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
2014-04-03powerpc/e6500: remove rev1 defconfigScott Wood
The SDK no longer supports rev1. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: Ief0e72d5305b16f994df3beca58134dd96e8aff7 Reviewed-on: http://git.am.freescale.net:8181/10273 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-03powerpc/e6500: Remove A-004801 workaroundScott Wood
The SDK no longer supports e6500 rev1. This reverts commit 38043080bb90f931efbe56a3f407c18206985f18 "powerpc/e6500: extend TLB miss lock to invalidations" and commit b9e282e1347b771b736a84e6b0a1048c551e6a6c "powerpc/e6500: add kconfig option for erratum A-004801" Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I749f497cbb6b96d045434065b869b253f01d6575 Reviewed-on: http://git.am.freescale.net:8181/10272 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-03Revert "powerpc/mpc85xx/e6500: work around CPU erratum A-006198"Scott Wood
This reverts commit f4c0e693ccc3422c5b809e7cc8f59b7637e3b7ab. rev1 is no longer supported in the SDK, and the workaround for A-006198 conflicts with machine check support. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: I64e1ce19eb59a6bba8649156597cc49ff9b62b1e Reviewed-on: http://git.am.freescale.net:8181/10271 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Kim Phillips <Kim.Phillips@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-03mtd:m25p80: Add device-id entry for Micron N25Q512A memoryPriyanka Jain
Add device-id entry for N25Q512A in device_id structure. Flash has following features: -64MB size, 1.8V, Mulitple I/O, 4KB Sector erase memory. -Memory is organised as 1024(64KB) main sectors. -Each sector is divided into 256 pages. -Register set/Opcodes are similar to other N25Q family products -Device ID: 20ba20 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Change-Id: Ifd191e1f2b0fb94ad7f37ff08dbf60f8e1617991 Reviewed-on: http://git.am.freescale.net:8181/10594 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-03uio: fix up fsl_sec_uio driver compilation errorHou Zhiqiang
| drivers/uio/fsl_sec_uio.c: In function 'fsl_sec_jr_probe': | drivers/uio/fsl_sec_uio.c:186:2: error: implicit declaration of function 'of_address_to_resource' [-Werror=implicit-function-declaration] | ret = of_address_to_resource(jr_node, 0, &regs); | ^ | drivers/uio/fsl_sec_uio.c:211:2: error: implicit declaration of function 'irq_of_parse_and_map' [-Werror=implicit-function-declaration] | jr->irq = irq_of_parse_and_map(jr_node, 0); | ^ | drivers/uio/fsl_sec_uio.c: In function 'fsl_sec_probe': | drivers/uio/fsl_sec_uio.c:296:2: error: implicit declaration of function 'of_iomap' [-Werror=implicit-function-declaration] | sec_dev->global_regs = of_iomap(sec_node, 0); Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Change-Id: I5bcaa4e15c48c7aa80edb478ac86ad1aa6f2eea4 Reviewed-on: http://git.am.freescale.net:8181/10591 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-03iommu/fsl: Enable default DMA window for PCIe devices once detached from domain.Varun Sethi
Once the PCIe device assigned to a guest VM (via VFIO) gets detached from the iommu domain (when guest terminates), its PAMU table entry is disabled. So, this would prevent the device from being used once it's assigned back to the host. This patch allows for creation of a default DMA window corresponding to the device and subsequently enabling the PAMU table entry. Before we enable the entry, we ensure that the device's bus master capability is disabled (device quiesced). Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: Iab4da4adfac8536a6834011431a395ba3a4982d2 Reviewed-on: http://git.am.freescale.net:8181/10257 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-03iommu/fsl: Factor out PCI specific code.Varun Sethi
Factor out PCI specific code in the PAMU driver. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: Ia6d73dca46b7274e14f7d7099aaef22d6510d1aa Reviewed-on: http://git.am.freescale.net:8181/10256 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-01Reduce reference count of DMA memory fragments during unmapRoy Pledge
If a process explictly unmapped DMA fragments the reference count of each fragement wasn't properly decremented causing a leak. This would only occur if the proccess explicitly umapped the memory, exiting the process did correctly adjust the reference counts Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com> Change-Id: Ia9adfccd5249d17d5506796b1fe71c32f46cab30 Reviewed-on: http://git.am.freescale.net:8181/10527 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-01gianfar: asf_gianfar will compile when CONFIG_GIANFAR is set.Alok Makhariya
asf_gianfar will compile only when CONFIG_GIANFAR and CONFIG_AS_FASTPATH are set. Replacing CONFIG_RX_TX_BUFF_XCHG with CONFIG_AS_FASTPATH and CONFIG_GIANFAR in skbuff structure of skbuff.h Removing CONFIG_RX_TX_BUFF_XCHG flag from kconfig. Change-Id: Iba0da980dfb807808cb3f9cd7d18a0229fa96b35 CR:ENGR00306399 Signed-off-by: Alok Makhariya <B46187@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10535 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-01Make the diu driver work without board level initializationJason Jin
So far the DIU driver does not have a mechanism to do the board specific initialization. So on some platforms, such as P1022, 8610 and 5121, The board specific initialization is implmented in the platform file such p10222_ds. Actually, the DIU is already intialized in the u-boot, the pin sharing and the signal routing are also set in u-boot. So we can leverage that in kernel driver to avoid board sepecific initialization, especially for the corenet platform, which is the abstraction for serveral platfroms. The potential problem is that when the system wakeup from the deep sleep, some platform settings may need to be re-initialized. The CPLD and FPGA settings will be kept, but the pixel clock register which usually locate at the global utility space need to be reinitialized. Generally, the pixel clock setting was implemented in the platform file, But the pixel clock register itself should be part of the DIU module, And for P1022,8610 and T1040, the pixel clock register have the same structure, So we can consider to move the pixel clock setting from the platform to the diu driver. This patch provide the options set the pixel clock in the diu driver. But the original platform pixel clock setting stil can be used for P1022,8610 and 512x without any update. To implement the pixel clock setting in the diu driver. the following update in the diu dts node was needed. display:display@180000 { compatible = "fsl,t1040-diu", "fsl,diu"; - reg = <0x180000 1000>; + reg = <0x180000 1000 0xfc028 4>; pixclk = <0 255 0>; interrupts = <74 2 0 0>; } The 0xfc028 is the offset for pixel clock register. the 3 segment of the pixclk stand for the PXCKDLYDIR, the max of PXCK and the PXCKDLY which will be used by the pixel clock register setting. This was tested on T1040 platform. For other platform, the original node together with the platform settings still can work. The binding update also included in this patch. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Change-Id: I0663914b08378fc7852eab788801f4e5dc59977d Reviewed-on: http://git.am.freescale.net:8181/10327 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-01uio: add support to map SRAM to userspaceHou Zhiqiang
This driver config the L2 Cache to be SRAM mode and map the SRAM to user space. The size and the address of SRAM are passed in the U-boot command line as format: cache-sram=addr,size. Please notice that this driver is exclusive with config FSL_85XX_CACHE_SRAM. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Change-Id: Ib0433acd459413fec5f5218751b0db79309895fd Reviewed-on: http://git.am.freescale.net:8181/10295 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Po Liu <Po.Liu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-04-01video/fsl: Fix the sleep function for FSL DIU moduleJason Jin
For deep sleep, the diu module will power off, when wake up from the deep sleep, more registers need to be reinitialized. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Change-Id: I3cffa545171a27391de0352aadcb871bc459e9dc Reviewed-on: http://git.am.freescale.net:8181/10328 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31Fix USDPAA DMA Mem freespace calculationRoy Pledge
The USDPAA DMA freespace calculation should only count segments with a reference count of zero as free Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com> Change-Id: Ib8752f8ad6cb4179b371b6480f47e84033260efe Reviewed-on: http://git.am.freescale.net:8181/10526 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31FMD: add PFC support for FMan v3 platformsCristian Bercaru
Configure up to 4 PFC priorities each with its PAUSE quanta. Each PFC priority controls a Work Queue on a FMan port. When the private interfaces' buffer pool depletes, there are issued PFC frames for the number of all configured priorities. Signed-off-by: Cristian Bercaru <cristian.bercaru@freescale.com> Change-Id: I8a6102f4a77b44d07973a38b98493226e9b69bbd Reviewed-on: http://git.am.freescale.net:8181/9767 Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com> Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com> Reviewed-by: Cristian-Constantin Sovaiala <Cristian.Sovaiala@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31dpaa_offload: New B4 DTS for ONIC integrationTibuleac Ioana-B41516
modifiy B4 DTS to support the ONIC integration in the ipsec_offload usecase Change-Id: I3a313d0dcfd8ed8aab22146d935696b96d3d670d Signed-off-by: Ioana Tibuleac <ioana.tibuleac@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10494 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Marian-Cornel Chereji <marian.chereji@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31dpa_eth: fix issue in dpa_release_sgt()Madalin Bucur
ARRAY_SIZE() was used on non-array parameter. Moved parameter inside function as it was not used outside. Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com> Change-Id: Icd84ece1b1c4762bcaacf426cbd58a285fa98063 Reviewed-on: http://git.am.freescale.net:8181/10435 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Cristian Bercaru <cristian.bercaru@freescale.com> Reviewed-by: Cristian-Constantin Sovaiala <Cristian.Sovaiala@freescale.com> Reviewed-by: Ruxandra Ioana Radulescu <ruxandra.radulescu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31crypto: caam - add support for gcm(aes)Tudor Ambarus
Add support for AES working in Galois Counter Mode. There is a limitation related to IV size, similar to the one present in SW implementation (crypto/gcm.c): The only IV size allowed is 12 bytes. It will be padded by HW to the right with 0x0000_0001 (up to 16 bytes - AES block size), according to the GCM specification. Change-Id: I3cca960678049bae3e387bc13f399c787ac6ac80 Signed-off-by: Tudor Ambarus <tudor.ambarus@freescale.com> Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10492 Reviewed-by: Mircea Pop <mircea.pop@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Alexandru Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31crypto: caam - add support for aead null encryptionHoria Geanta
Add support for the following combinations: -encryption: null -authentication: md5, sha* (1, 224, 256, 384, 512) Change-Id: I610815e59527b75277d8af45bac4b37467ac24c0 Signed-off-by: Tudor Ambarus <tudor.ambarus@freescale.com> Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10491 Reviewed-by: Mircea Pop <mircea.pop@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Alexandru Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31crypto: testmgr - add aead null encryption test vectorsHoria Geanta
Add test vectors for aead with null encryption and md5, respectively sha1 authentication. Input data is taken from test vectors listed in RFC2410. Change-Id: I7e5040647dc21bac51f69a450b9d87fca7d441ee Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10490 Reviewed-by: Mircea Pop <mircea.pop@freescale.com> Reviewed-by: Tudor-Dan Ambarus <tudor.ambarus@freescale.com> Reviewed-by: Alexandru Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31crypto: export NULL algorithms definesHoria Geanta
These defines might be needed by crypto drivers. Change-Id: Ic9dee056b7ec9bfa968bcd85c150046e30e260b6 Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10489 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tudor-Dan Ambarus <tudor.ambarus@freescale.com> Reviewed-by: Alexandru Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31crypto: caam - remove error propagation handlingHoria Geanta
Commit 61bb86bba169507a5f223b94b9176c32c84b4721 ("crypto: caam - set descriptor sharing type to SERIAL") changed the descriptor sharing mode from SHARE_WAIT to SHARE_SERIAL. All descriptor commands that handle the "ok to share" and "error propagation" settings should also go away, since they have no meaning for SHARE_SERIAL. Change-Id: Ia4343fec64b653fa231abca7cd2660c0b653c8b1 Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10488 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tudor-Dan Ambarus <tudor.ambarus@freescale.com> Reviewed-by: Alexandru Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31crypto: caam - add missing key_dma unmapHoria Geanta
(struct caam_ctx) ctx->key_dma needs to be unmapped when context is cleaned up. Change-Id: I547568ab769a88241970950dad56666b4acf5516 Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10487 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mircea Pop <mircea.pop@freescale.com> Reviewed-by: Tudor-Dan Ambarus <tudor.ambarus@freescale.com> Reviewed-by: Alexandru Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31crypto: caam/qi - fix missing coma typoHoria Geanta
Change-Id: I7beafae40b9d535595f7e693eb23aa17425c5fd8 Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10486 Reviewed-by: Mircea Pop <mircea.pop@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tudor-Dan Ambarus <tudor.ambarus@freescale.com> Reviewed-by: Cristian Stoica <cristian.stoica@freescale.com> Reviewed-by: Alexandru Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31net/phy: add PM for ar8033Zhao Qiang
add suspend and resume functions for ar8033 Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I7e3817ae3addff45901d8ef96c3c98d0c9eef56e Reviewed-on: http://git.am.freescale.net:8181/10508 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31powerpc/mpic: supply a .disable callbackChenhui Zhao
Currently MPIC provides .mask, but not .disable. This means that effectively disable_irq() soft-disables the interrupt, and you get a .mask call if an interrupt actually occurs. I'm not sure if this was intended as a performance benefit (it seems common to omit .disable on powerpc interrupt controllers, but nowhere else), but it interacts badly with threaded/workqueue interrupts (including KVM reflection). In such cases, where the real interrupt handler does a disable_irq_nosync(), schedules defered handling, and returns, we get two interrupts for every real interrupt. The second interrupt does nothing but see that IRQ_DISABLED is set, and decide that it would be a good idea to actually call .mask. In the sleep case, disable all irqs of IP blocks using .disable() when entering sleep. Change-Id: I8f57e20a87acae115d0a8a006d31ffdedb42c295 Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10507 Reviewed-by: Yang Li <LeoLi@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31dpa_offload: Add SA per DSCP support in DPA IPSecAurelian Zanoschi
If different classes of traffic defined by DSCP are sent on the same SA and if the receiver is using an optional anti-replay feature, this could result in discarding lower priority packets. To avoid this, the sender should send traffic with different classes, but the same selector values on different SA's in order to support QoS appropriately. The IPSec implementation must permit establishment and maitenance of multuple SA's between sender and receiver, with the same selectors. The receiver must process the packets from the different SAs without prejudice. These requirements apply to both transport and tunnel mode SA's. (RFC-4301) On IPSec inbound path there are no needed modifcations in order to support this feature. The idea behind this feature is to direct outbount traffic with different DSCP to different outbound SA's, even if it has the same SA selector with the rest of the traffic. On the outbound direction the selectors for the policies are partially custom. Now the user can select fields from the following group of supported fields: * IPSA (supports mask) * IPDA (supports mask) * IPPROTO * DSCP * SPORT (for TCP/UDP/SCTP) * DPORT (for TCP/UDP/SCTP) * ICMP_TYPE * ICMP_CODE The format of the key is fixed and cannot be modified, but the user has the possibility to mask the fields wants to use in the policy selector. For the DSCP field, the user can set a range of values between dscp_start and dscp_end. The DPA IPSec will create a policy selector for every DSCP value entered by the user. In case dscp_start equals dscp_end, only one policy will be added. This requires the user to properly configure the outbound pre-SEC CC nodes to generate the key using also the DSCP field. The statistics returned for the SA with a range of DSCP values defined, will totalize the statistics for every policy selector. Change-Id: I96c1629ca2d52bc6023af494929e27865348230a Signed-off-by: Aurelian Zanoschi <Aurelian.Zanoschi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9874 Reviewed-by: Marian-Cornel Chereji <marian.chereji@freescale.com> Reviewed-by: Andrei Varvara <andrei.varvara@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31gianfar: Allocate extra headroom while allocating skb in gianfarAlok Makhariya
ASF requires some extra headrom for IPSec processing. During IPSec processing packet size increases adding the Outer IP header, ESP header, ICV and Padding to the packet. In case the headroom/tailroom is not present copy of packet is made. Reserved that required extra headroom while allocating the buffer in gianfar, so that packet copy is avoided CQ ID : ENGR00304852 Change-Id: I2580bf20fb2acd5a9ced4166375ca22f56f764fe Signed-off-by: Alok Makhariya <B46187@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10356 Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31asf : support ASF in minimal modeAlok Makhariya
gfar_fast_xmit function is added in asf_gianfar.c to support minimal mode in ASF. Change-Id: I4556e8f55400bf1eb0ed858b38df805522b6bd12 CQ ID : ENGR00304852 Signed-off-by: Alok Makhariya <B46187@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10355 Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31asf_gianfar: adding selective skb cleanup for asf processed pktAlok Makhariya
CQ ID : ENGR00304852 Signed-off-by: Alok Makhariya <B46187@freescale.com> Change-Id: Ifa4463e3c1eda512d9f2504eba42c8358b11c1ff Reviewed-on: http://git.am.freescale.net:8181/10485 Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31ASF : Adding hooks to offload packets to ASFAlok Makhariya
Hooks are added in asf_gianfar.c to offload packet to ASF. Change-Id: Id553d25510d18d7918d02e8375c5fc89d7e6e9a1 CQ ID : ENGR00304852 Signed-off-by: Alok Makhariya <B46187@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10354 Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31gianfar: Calling ASF specific xmit and rx_ring_cleanup functionsAlok Makhariya
xmit and rx_ring_cleanup function in asf_gianfar.c are called from gianfar.c Change-Id: If44afeba7843a484cbd8c144b64e4e1cfe9fe331 CQ ID : ENGR00304852 Signed-off-by: Alok Makhariya <B46187@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10352 Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Reviewed-by: Claudiu Manoil <claudiu.manoil@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-31ASF : Adding ASF specific gianfar xmit and clean_rx_ringAlok Makhariya
New file asf_gianfar.c and asf_gianfar.h is added to support ASF. CQ ID : ENGR00304852 Change-Id: I44829148111a067476fe212aadcecdbc088e5091 Signed-off-by: Alok Makhariya <B46187@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10351 Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Reviewed-by: Claudiu Manoil <claudiu.manoil@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
generated by cgit v0.10.2 at 2024-07-06 01:29:44 (GMT)