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cache-l2x0.c
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Author
2013-09-05
Merge branches 'debug-choice', 'devel-stable' and 'misc' into for-linus
Russell King
2013-08-19
ARM: 7821/1: DT: binding fixup to align with vendor-prefixes.txt
Christian Daudt
2013-08-19
ARM: 7820/1: mm: cache-l2x0: Print the cache size in kB
Fabio Estevam
2013-08-12
ARM: l2x0: use -st dsb option for ordering writel_relaxed with unlock
Will Deacon
2013-05-15
ARM: 7716/1: bcm281xx: Add L2 support for Rev A2 chips
Christian Daudt
2013-04-03
ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug ...
Rob Herring
2013-01-07
ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writel
Gregory CLEMENT
2013-01-07
ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT en...
Gregory CLEMENT
2013-01-02
ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier
Rob Herring
2012-11-06
ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrl
Gregory CLEMENT
2012-10-18
ARM: 7545/1: cache-l2x0: make outer_cache_fns a field of l2x0_of_data
Gregory CLEMENT
2012-10-07
Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm
Linus Torvalds
2012-09-15
ARM: 7507/1: cache-l2x0.c: save the final aux ctrl value for resuming
Yilu Mao
2012-09-11
ARM: cache-l2x0: add a const qualifier
Uwe Kleine-König
2012-04-23
ARM: 7398/1: l2x0: only write to debug registers on PL310
Will Deacon
2012-04-23
ARM: 7397/1: l2x0: only apply workaround for erratum #753970 on PL310
Will Deacon
2012-01-20
ARM: cache-l2x0.c: consistently use u32
Russell King
2011-11-21
ARM: 7162/1: errata: tidy up Kconfig options for PL310 errata workarounds
Will Deacon
2011-10-26
Merge branch 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/k...
Linus Torvalds
2011-10-17
ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure mode
Barry Song
2011-10-17
ARM: 7090/1: CACHE-L2X0: filter start address can be 0 and is often 0
Barry Song
2011-10-17
ARM: 7089/1: L2X0: add explicit cpu_relax() for busy wait loop
Barry Song
2011-10-17
ARM: 7009/1: l2x0: Add OF based initialization
Rob Herring
2011-09-13
locking, ARM: Annotate low level hw locks as raw
Thomas Gleixner
2011-09-06
ARM: 7080/1: l2x0: make sure I&D are not locked down on init
Linus Walleij
2011-07-06
ARM: 6987/1: l2x0: fix disabling function to avoid deadlock
Will Deacon
2011-03-16
Merge branch 'misc' into devel
Russell King
2011-03-09
ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corrupti
Santosh Shilimkar
2011-02-19
ARM: 6741/1: errata: pl310 cache sync operation may be faulty
Srinidhi Kasagar
2010-10-26
ARM: l2x0: Optimise the range based operations
Santosh Shilimkar
2010-10-26
ARM: l2x0: Determine the cache size
Santosh Shilimkar
2010-10-26
arm: Implement l2x0 cache disable functions
Thomas Gleixner
2010-10-26
ARM: Improve the L2 cache performance when PL310 is used
Catalin Marinas
2010-07-29
ARM: 6272/1: Convert L2x0 to use the IO relaxed operations
Catalin Marinas
2010-07-09
ARM: 6210/1: Do not rely on reset defaults of L2X0_AUX_CTRL
Sascha Hauer
2010-05-17
Merge branch 'devel-stable' into devel
Russell King
2010-05-15
ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310
Jason McMullan
2010-03-25
ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)
Catalin Marinas
2010-02-15
ARM: 5919/1: ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate cl...
Santosh Shilimkar
2010-02-15
ARM: 5916/1: ARM: L2 : Add maintainace by line helper functions
Santosh Shilimkar
2009-12-14
Merge branch 'pending-l2x0' into cache
Russell King
2009-12-14
ARM: cache-l2x0: make better use of background cache handling
Russell King
2009-12-14
ARM: cache-l2x0: avoid taking spinlock for every iteration
Russell King
2009-12-03
ARM: 5845/1: l2x0: check whether l2x0 already enabled
Srinidhi Kasagar
2008-09-06
[ARM] Convert asm/io.h to linux/io.h
Russell King
2007-09-17
[ARM] 4568/1: fix l2x0 cache invalidate handling of unaligned addresses
Rui Sousa
2007-07-20
[ARM] 4500/1: Add locking around the background L2x0 cache operations
Catalin Marinas
2007-02-11
[ARM] 4135/1: Add support for the L210/L220 cache controllers
Catalin Marinas