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path: root/arch/arm/mm/cache-v7.S
AgeCommit message (Expand)Author
2012-10-11Merge branch 'fixes' into for-linusRussell King
2012-09-28ARM: 7541/1: Add ARM ERRATA 775420 workaroundSimon Horman
2012-09-25ARM: mm: rename jump labels in v7_flush_dcache_all functionLorenzo Pieralisi
2012-09-25ARM: mm: implement LoUIS API for cache maintenance opsLorenzo Pieralisi
2012-05-02ARM: 7408/1: cacheflush: return error to userspace when flushing syscall failsWill Deacon
2012-02-15ARM: 7325/1: fix v7 boot with lockdep enabledRabin Vincent
2012-02-09ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDRStephen Boyd
2011-09-17ARM: 7091/1: errata: D-cache line maintenance operation by MVA may not succeedWill Deacon
2011-07-07ARM: mm: cache-v7: Use the new processor struct macrosDave Martin
2011-05-26ARM: 6941/1: cache: ensure MVA is cacheline aligned in flush_kern_dcache_areaWill Deacon
2011-03-31Fix common misspellingsLucas De Marchi
2010-12-12ARM: 6528/1: Use CTR for the I-cache line size on ARMv7Catalin Marinas
2010-10-04ARM: 6405/1: Handle __flush_icache_all for CONFIG_SMP_ON_UPTony Lindgren
2010-10-04ARM: Allow SMP kernels to boot on UP systemsRussell King
2010-05-20ARM: 6139/1: ARMv7: Use the Inner Shareable I-cache on MPSantosh Shilimkar
2010-05-08ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMPCatalin Marinas
2010-02-15ARM: dma-mapping: fix for speculative prefetchingRussell King
2010-02-15ARM: dma-mapping: remove dmac_clean_range and dmac_inv_rangeRussell King
2010-02-15ARM: dma-mapping: provide per-cpu type map/unmap functionsRussell King
2009-12-14ARM: add size argument to __cpuc_flush_dcache_pageRussell King
2009-10-07ARM: 5746/1: Handle possible translation errors in ARMv6/v7 coherent_user_rangeCatalin Marinas
2009-07-24Thumb-2: Implement the unified arch/arm/mm supportCatalin Marinas
2008-11-06ARMv7: Add extra barriers for flush_cache_all compressed/head.SCatalin Marinas
2008-09-01[ARM] 5227/1: Add the ENDPROC declarations to the .S filesCatalin Marinas
2007-05-08[ARM] armv7: add support for ARMv7 cores.Catalin Marinas
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