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From Jason Cooper:
mvebu drivers changes for v3.12
- MBus devicetree bindings
- devbus update for address decoding window, cleanup
* tag 'drivers-3.12' of git://git.infradead.org/linux-mvebu: (35 commits)
memory: mvebu-devbus: Remove unused variable
ARM: mvebu: Relocate PCIe node in Armada 370 RD board
ARM: mvebu: Fix AXP-WiFi-AP DT for MBUS DT binding
ARM: mvebu: add support for the AXP WiFi AP board
ARM: mvebu: use dts pre-processor for mv78230
PCI: mvebu: Adapt to the new device tree layout
bus: mvebu-mbus: Add devicetree binding
ARM: kirkwood: Relocate PCIe device tree nodes
ARM: kirkwood: Introduce MBUS_ID
ARM: kirkwood: Introduce MBus DT node
ARM: kirkwood: Use the preprocessor on device tree files
ARM: kirkwood: Split DT and legacy MBus initialization
ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes
ARM: mvebu: Relocate Armada 370/XP DeviceBus device tree nodes
ARM: mvebu: Add BootROM to Armada 370/XP device tree
ARM: mvebu: Add MBus to Armada 370/XP device tree
ARM: mvebu: Use the preprocessor on Armada 370/XP device tree files
ARM: mvebu: Initialize MBus using the DT binding
ARM: mvebu: Remove the harcoded BootROM window allocation
bus: mvebu-mbus: Factorize Armada 370/XP data structures
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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If CONFIG_FRAME_POINTER=y we get the following error:
arch/arm/mach-vexpress/tc2_pm.c: In function 'tc2_pm_down':
arch/arm/mach-vexpress/tc2_pm.c:200:1: error: fp cannot be used in asm here
Let's fix that by explicitly preserving r11 on the stack and removing it
from the clobber list.
Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Second Round of Renesas ARM based SoC updates for v3.12
* Increased clock coverage for r8a7740 and r8a7790 SoCs
* tag 'renesas-soc2-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7740: Add TPU clock entry for DT platforms
ARM: shmobile: r8a7790: clocks for Ether support
ARM: shmobile: r8a7740: Fix TPU clock name
ARM: shmobile: Insert align directives before 4 bytes data
ARM: shmobile: Force ARM mode to compile reset vector for secondary CPUs
ARM: shmobile: fix compile error when CONFIG_THUMB2_KERNEL=y
ARM: shmobile: Update romImage to relocate appended DTB
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Renesas ARM based SoC updates for v3.12
* Setup arch timer based on MD pins on r8a7790 SoC
* Thermal driver support for r8a7790 SoC
* Make arch timer optional for r8a7790 and r8a73a4 SoCs
* CMT10 clock event for r8a7790 and r8a73a4 SoCs
* Increased clock coverage for r8a73a4 SoC
* MMCIF DMA definitions for r8a7740 SoC
* Disconnect SMP code from clocks on emev2 SoC
* tag 'renesas-soc-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (49 commits)
ARM: shmobile: Setup r8a7790 arch timer based on MD pins
ARM: shmobile: Introduce r8a7790_read_mode_pins()
ARM: shmobile: r8a7740: add MMCIF DMA definitions
ARM: shmobile: Disconnect EMEV2 SMP code from clocks
ARM: shmobile: Make r8a73a4 Arch timer optional
ARM: shmobile: Add r8a73a4 CMT10 clock event
ARM: shmobile: Make r8a7790 Arch timer optional
ARM: shmobile: Add r8a7790 CMT00 clock event
ARM: shmobile: Sort r8a7790 MSTP entries
ARM: shmobile: r8a73a4: add clocks for I2C controllers
ARM: shmobile: r8a73a4: add Z2 clock support
ARM: shmobile: r8a73a4: safeguard against wrong clk_set_rate() uses
ARM: shmobile: r8a73a4: implement CPU clock scaling for CPUFreq
ARM: shmobile: r8a73a4: wait for completion when kicking the clock
ARM: shmobile: r8a7790: add thermal driver support
ARM: shmobile: r8a7790: add clocks for thermal
ARM: shmobile: Add SMSC ethernet chip to KZM9D DT reference
ARM: shmobile: KZM9D DT reference implementation
ARM: shmobile: r8a7790: add MMCIF and SDHI DT templates
ARM: shmobile: r8a73a4: add MMCIF and SDHI DT templates
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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This will delete some redundant calling of sirfsoc_of_pwrc_init() and
sirfsoc_memc_init() for non-CSR platforms if we use multi-platform.
Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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This patch also enables RTC alarm as wakeup source after system suspends.
Signed-off-by: Xianglong Du <Xianglong.Du@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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The pcie-controller node needs to be relocated according the MBus
DT binding, since it's now a child of the mbus-compatible node.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The ranges property needs to be changed to use the new MBus DT binding.
Also, the pcie-controller node needs to be relocated as according the MBus
DT binding, it's now a child of the mbus-compatible node.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The AXP WiFi AP board is a Marvell platform based on the Armada XP
MV78230 SoC. It has two mini-PCIe connectors, one USB 3.0 port powered
by a USB 3.0 controller on PCIe, two Ethernet ports, 1 GB of RAM, 1 GB
of NAND, 16 MB of SPI flash, one SATA port and one button, two UARTs
Successfully tested: USB 3.0 port, the mini-PCIe connectors, SPI
flash, Ethernet ports, SATA port, button, UART.
Untested: NAND flash, due to lack of mainline support for the Armada
370/XP NAND controller for now.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Seif Mazareeb <seif@marvell.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Similar to power_down(), except that for a suspend, the firmware
mailbox address has to be set prior entering low power mode.
The residency argument is not used yet, so the last man always shuts
down the cluster for now.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Pawel Moll <pawel.moll@arm.com>
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This is the MCPM backend for the Virtual Express A15x2 A7x3 CoreTile
aka TC2. This provides cluster management for SMP secondary boot and
CPU hotplug.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[PM: made it drive SCC registers directly and provide base for SPC]
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
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SCC (Serial Configuration Controller) is used to set initial
conditions for the test chip (TC2). Its registers are also mapped
in normal address space and used to obtain runtime information
and for power management.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
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The TC2 versatile express core tile integrates a logic block that provides
the interface between the dual cluster test-chip and the M3 microcontroller
that carries out power management. The logic block, called Serial Power
Controller (SPC), contains several memory mapped registers to control among
other things low-power states, wake-up irqs and per-CPU jump addresses
registers.
This patch provides a driver that enables run-time control of features
implemented by the SPC power management control logic with an API to
be used by different subsystem drivers on top.
The SPC control logic is required to be programmed very early in the boot
process to reset secondary CPUs on the TC2 testchip, set-up jump addresses
and wake-up IRQs for power management. Hence, waiting for core changes to
be made in the device core code to enable early registration of platform
devices, the driver puts in place an early init scheme that allows kernel
drivers to initialize the SPC driver directly from the components requiring
it, if their initialization routine is called before this driver init
function during the boot process.
Device tree bindings documentation for the SPC component is also provided.
Cc: Olof Johansson <olof@lixom.net>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
[ np: moved from drivers/mfd/ to drivers/platform/vexpress/ ]
Signed-off-by: Nicolas Pitre <nico@linaro.org>
[ PM: moved again to arch/arm/mach-vexpress, requested by Olof ]
[ PM: removed useless printk, from Olof ]
[ PM: made the driver SPC-only ]
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
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Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of the ocp node, placing it directly
below the mbus. This is a more accurate representation of the hardware.
Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to
correspond to each MBus window.
In addition, we encode the PCIe memory and I/O apertures in the MBus
node, according to the MBus DT binding specification. The choice made
is 0xe0000000-0xf0000000 for memory space, and 0xf200000-0xf2100000 for
I/O space. These apertures can be changed in each per-board DT file.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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This macro is used to define window's target ID and attribute cells
for the MBus ranges entries.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Add a minimal MBus node, just to allow the MBus driver to probe.
Follow-up patches will migrate the rest of the nodes appropriately.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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This commit replaces the legacy MBus initialization with the new
DT-based in Kirkwood. For boards that are not yet converted to DT,
we keep the legacy initialization.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the
hardware.
Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to correspond
to each MBus window.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Now that mbus has been added to the device tree, it's possible to
move the DeviceBus out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the hardware.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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In order to access the SoC BootROM, we need to declare a mapping
(through a ranges property). The mbus driver will use this property
to allocate a suitable address decoding window.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The Armada 370/XP SoC family has a completely configurable address
space handled by the MBus controller.
This patch introduces the device tree layout of MBus, making the
'soc' node as mbus-compatible.
Since every peripheral/controller is a child of this 'soc' node,
this makes all of them sit behind the mbus, thus describing the
hardware accurately.
A translation entry has been added for the internal-regs mapping.
This can't be done in the common armada-370-xp.dtsi because A370
and AXP have different addressing width.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Now that the mbus device tree binding has been introduced, we can
switch over to it.
Also, and since the initialization of the mbus driver is quite
fundamental for the system to work properly, this patch adds a BUG()
in case mbus fails to initialize.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The address decoding window to access the BootROM should not be
allocated programatically, but instead declared in the device tree.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Renesas ARM based SoC fixes for v3.12
* Fix TPU clock name for r8a7740 SoC
* Update romImage to relocate appended DTB
* Thumb fixes
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Unlike real A15/A7's, the RTSM simulation doesn't appear to hit the
cache when the CTRL.C bit is cleared. Let's ensure there is no memory
access within the disable and flush cache sequence, including to the
stack.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull power management and ACPI fixes from Rafael Wysocki:
"These are fixes collected over the last week, most importnatly two
cpufreq reverts fixing regressions introduced in 3.10, an autoseelp
fix preventing systems using it from crashing during shutdown and two
ACPI scan fixes related to hotplug.
Specifics:
- Two cpufreq commits from the 3.10 cycle introduced regressions.
The first of them was buggy (it did way much more than it needed to
do) and the second one attempted to fix an issue introduced by the
first one. Fixes from Srivatsa S Bhat revert both.
- If autosleep triggers during system shutdown and the shutdown
callbacks of some device drivers have been called already, it may
crash the system. Fix from Liu Shuo prevents that from happening
by making try_to_suspend() check system_state.
- The ACPI memory hotplug driver doesn't clear its driver_data on
errors which may cause a NULL poiter dereference to happen later.
Fix from Toshi Kani.
- The ACPI namespace scanning code should not try to attach scan
handlers to device objects that have them already, which may
confuse things quite a bit, and it should rescan the whole
namespace branch starting at the given node after receiving a bus
check notify event even if the device at that particular node has
been discovered already. Fixes from Rafael J Wysocki.
- New ACPI video blacklist entry for a system whose initial backlight
setting from the BIOS doesn't make sense. From Lan Tianyu.
- Garbage string output avoindance for ACPI PNP from Liu Shuo.
- Two Kconfig fixes for issues introduced recently in the s3c24xx
cpufreq driver (when moving the driver to drivers/cpufreq) from
Paul Bolle.
- Trivial comment fix in pm_wakeup.h from Chanwoo Choi"
* tag 'pm+acpi-3.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm:
ACPI / video: ignore BIOS initial backlight value for Fujitsu E753
PNP / ACPI: avoid garbage in resource name
cpufreq: Revert commit 2f7021a8 to fix CPU hotplug regression
cpufreq: s3c24xx: fix "depends on ARM_S3C24XX" in Kconfig
cpufreq: s3c24xx: rename CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
PM / Sleep: Fix comment typo in pm_wakeup.h
PM / Sleep: avoid 'autosleep' in shutdown progress
cpufreq: Revert commit a66b2e to fix suspend/resume regression
ACPI / memhotplug: Fix a stale pointer in error path
ACPI / scan: Always call acpi_bus_scan() for bus check notifications
ACPI / scan: Do not try to attach scan handlers to devices having them
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The TPU device is called renesas-tpu-pwm, not renesas_tpu_pwm. Fix the
clock name accordingly.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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In thumb2 mode instructions are not align to 4 byte. This patch insert
align directives before putting 4 byte data.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Instructions start from boot vector must be ARM mode.
This patch specify ARM mode explicitly and use 'bx' instruction to be
able to change to Thumb mode.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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On KZM-A9-GT board (SMP), when CONFIG_THUMB2_KERNEL=y it fails to compile
AS arch/arm/mach-shmobile/headsmp-scu.o
/proj/koba/kernel/arm-soc/arch/arm/mach-shmobile/headsmp-scu.S: Assembler messages:
/proj/koba/kernel/arm-soc/arch/arm/mach-shmobile/headsmp-scu.S:41: Error: shift must be constant -- `bic r2,r2,r3,lsl r1'
make[2]: *** [arch/arm/mach-shmobile/headsmp-scu.o] Error 1
make[1]: *** [arch/arm/mach-shmobile] Error 2
make: *** [sub-make] Error 2
Instruction `bic r2,r2,r3,lsl r1' is not supported in thumb mode. This patch split it into 2 instructions.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Update the r8a7790 arch timer setup code to configure the
frequency dynamically at boot time. This means that the arch
timer driver will be able to detect a timer frequency that
has been calculated based on the MD pins instead of a fixed
and potentially incorrect 13 MHz.
With this patch applied the Linux kernel will correctly
support the r8a7790 Lager board that uses a 20 Mhz EXTAL.
The arch timer will operate on 10 MHz and the Linux arch
timer driver will be correctly configured to use 10 MHz.
Without this patch the 20 MHz EXTAL will be used to drive
the arch timer at 10 MHz, but the Linux arch timer driver
will believe it is counting at 13 Mhz.
Reported-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Ulrich Hecht <ulrich.hecht@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Break out the r8a7790 boot mode code into a separate
function so it can be shared by multiple users.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add DMA channel slave IDs and configuration entries for the r8a7740
MMCIF controller.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Update the EMEV2 SMP code to access the SMU directly
instead of relying on help from the legacy clock code.
This change moves us one step closer to common clocks.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Update the r8a73a4 code to allow using other
timers than Arch timer for clock event
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add clock event support for CMT1 timer channel 0
to the r8a73a4 SoC code. The CMT is used together
with a 32KHz clock in this case.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Update the r8a7790 code to allow using other
timers than Arch timer for clock events.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add clock event support for CMT0 timer channel 0
to the r8a7790 SoC code. On most ARM mach-shmobile
the CMT is hooked up to a 32KHz clock but on r8a7790
a 31.7KHz clock is instead used.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The r8a7790 MSTP bits should be kept sorted in the same way
as on other mach-shmobile SoCs. Move the HSCIF and thermal
bits to clean up the current state.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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r8a73a4 SoCs have numerous I2C controllers, of which 9 are compatible with
the i2c-sh_mobile.c driver. This patch adds clock definitions for them.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The Z2 clock on r8a73a4 is used to clock the 4 Cortex A7 cores on the SoC.
Add a definition for this clock to later use it from the arm_big_little
CPUFreq driver.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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