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2013-07-14MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-09MIPS: Move 'gic_present' to common location.Steven J. Hill
Move the global variable 'gic_present' to be defined in the file 'arch/mips/kernel/irq-gic.c' instead of defining it individually for each platform making use of the GIC. Also change the type to be an unsigned integer instead of signed. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-08-22MIPS: Fix build error for non-malta VSMP kernelAnoop P A
VSMP kernel build for non-malta platforms fails with following error LD init/built-in.o LD .tmp_vmlinux1 arch/mips/built-in.o: In function `vsmp_init_secondary': smp-mt.c:(.cpuinit.text+0x23cc): undefined reference to `gic_present' smp-mt.c:(.cpuinit.text+0x23d0): undefined reference to `gic_present' make: *** [.tmp_vmlinux1] Error 1 gic_present variable is declared only if IRQ_GIC is selected. Signed-off-by: Anoop P A <anoop.pa@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/2039/ Signed-off-by: John Crispin <blogic@openwrt.org>
2012-03-28Disintegrate asm/system.h for MIPSDavid Howells
Disintegrate asm/system.h for MIPS. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> cc: linux-mips@linux-mips.org
2011-07-26atomic: use <linux/atomic.h>Arun Sharma
This allows us to move duplicated code in <asm/atomic.h> (atomic_inc_not_zero() for now) to <linux/atomic.h> Signed-off-by: Arun Sharma <asharma@fb.com> Reviewed-by: Eric Dumazet <eric.dumazet@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: David Miller <davem@davemloft.net> Cc: Eric Dumazet <eric.dumazet@gmail.com> Acked-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-03-31Fix common misspellingsLucas De Marchi
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
2010-12-16MIPS: MT: Fix typo in comment.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-24cpumask: Use accessors for cpu_*_mask: mipsRusty Russell
Use the accessors rather than frobbing bits directly (the new versions are const). Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Mike Travis <travis@sgi.com>
2009-09-24cpumask: arch_send_call_function_ipi_mask: mipsRusty Russell
We're weaning the core code off handing cpumask's around on-stack. This introduces arch_send_call_function_ipi_mask(), and by defining it, the old arch_send_call_function_ipi is defined by the core code. We also take the chance to wean the implementations off the obsolescent for_each_cpu_mask(): making send_ipi_mask take the pointer seemed the most natural way to ensure all implementations used for_each_cpu. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
2008-12-13cpumask: centralize cpu_online_map and cpu_possible_mapRusty Russell
Impact: cleanup Each SMP arch defines these themselves. Move them to a central location. Twists: 1) Some archs (m32, parisc, s390) set possible_map to all 1, so we add a CONFIG_INIT_ALL_POSSIBLE for this rather than break them. 2) mips and sparc32 '#define cpu_possible_map phys_cpu_present_map'. Those archs simply have phys_cpu_present_map replaced everywhere. 3) Alpha defined cpu_possible_map to cpu_present_map; this is tricky so I just manipulate them both in sync. 4) IA64, cris and m32r have gratuitous 'extern cpumask_t cpu_possible_map' declarations. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Tested-by: Tony Luck <tony.luck@intel.com> Acked-by: Ingo Molnar <mingo@elte.hu> Cc: Mike Travis <travis@sgi.com> Cc: ink@jurassic.park.msu.ru Cc: rmk@arm.linux.org.uk Cc: starvik@axis.com Cc: tony.luck@intel.com Cc: takata@linux-m32r.org Cc: ralf@linux-mips.org Cc: grundler@parisc-linux.org Cc: paulus@samba.org Cc: schwidefsky@de.ibm.com Cc: lethal@linux-sh.org Cc: wli@holomorphy.com Cc: davem@davemloft.net Cc: jdike@addtoit.com Cc: mingo@redhat.com
2008-04-28[MIPS] Add support for MIPS CMP platform.Ralf Baechle
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28[MIPS] Remove TLB sanitation codeChris Dearman
It is not being used by Malta and shouldn't be needed for MIPSsim. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29[MIPS] SMP: Call platform methods via ops structure.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29[MIPS] MT: Scheduler support for SMTRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11[MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27[MIPS] SMP: Scatter __cpuinit over the code as needed.Ralf Baechle
MIPS doesn't do CPU hotplugging yet but since many of the functions don't even have an __init let's fix this right. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-04[MIPS] VSMP: Fix initialization ordering bug.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-14[MIPS] Separate performance counter interruptsChris Dearman
Support for performance counter overflow interrupt that is on a separate interrupt from the timer. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06[MIPS] Define MIPS_CPU_IRQ_BASE in generic headerAtsushi Nemoto
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-30[MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irqAtsushi Nemoto
Further incorporation of generic irq framework. Replacing __do_IRQ() by proper flow handler would make the irq handling path a bit simpler and faster. * use generic_handle_irq() instead of __do_IRQ(). * use handle_level_irq for obvious level-type irq chips. * use handle_percpu_irq for irqs marked as IRQ_PER_CPU. * setup .eoi routine for irq chips possibly used with handle_percpu_irq. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-10-31[MIPS] VSMP: Synchronize cp0 counters on bootup.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-10-31[MIPS] VSMP: Fix initialization ordering bug.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-10-08[MIPS] Complete fixes after removal of pt_regs argument to int handlers.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27[MIPS] MT: Initialise all writable bits in Cause register to zero.Chris Dearman
Recent 34Ks come out of reset with WP enabled on VPE 1 so we take an immediate exception when starting the second VPE. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-02[PATCH] irq-flags: MIPS: Use the new IRQF_ constantsThomas Gleixner
Use the new IRQF_ constants and remove the SA_INTERRUPT define Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@elte.hu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-19[MIPS] FPU affinity for MT ASE.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19[MIPS] MT: Improved multithreading support.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>