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2014-12-11qe: move qe from arch/powerpc/sysdev/ to drivers/soc/Zhao Qiang
ls1 has qe ip block too, so move qe code from platform directory to public directory. Signed-off-by: Zhao Qiang <B45475@freescale.com> --- patch on upstream can be found with this link: http://patchwork.ozlabs.org/patch/385724/, it is under discussion Change-Id: I39aed531a4792990e3bb8ecc6f4e57f8d9b41bae Reviewed-on: http://git.am.freescale.net:8181/15818 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-04-29fsl/pci: The new pci suspend/resume implementationWang Dongsheng
If we do nothing in suspend/resume, some platform PCIe ip-block can't guarantee the link back to L0 state from sleep, then, when we read the EP device will hang. Only we send pme turnoff message in pci controller suspend, and send pme exit message in resume, the link state will be normal. When we send pme turnoff message in pci controller suspend, the links will into l2/l3 ready, then, host cannot communicate with ep device, but pci-driver will call back EP device to save them state. So we need to change platform_driver->suspend/resume to syscore->suspend/resume. So the new suspend/resume implementation, send pme turnoff message in suspend, and send pme exit message in resume. And add a PME handler, to response PME & message interrupt. Change platform_driver->suspend/resume to syscore->suspend/resume. pci-driver will call back EP device, to save EP state in pci_pm_suspend_noirq, so we need to keep the link, until pci_pm_suspend_noirq finish. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: Id82d2e92994e466de1b2a4eb9ecef73c112ec753 Reviewed-on: http://git.am.freescale.net:8181/11538 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24split function mpc85xx_qe_init() into two functions.Zhao Qiang
micro QE is a kind of cutted QE, it has only 2 UCCs while normal QE has up to 8 UCCs. micro QE doesn't have par_io, it doesn't need to init par_io for micro QE. Split function mpc85xx_qe_init() into mpc85xx_qe_init() and mpc85xx_qe_par_io_init(). Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I267d044d6b0c6ff1c4bba984566d430e6b3dc682 Reviewed-on: http://git.am.freescale.net:8181/10098 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24powerpc/85xx: Add QE common init functionZhao Qiang
Define a QE init function in common file, and avoid the same codes being duplicated in board files. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I394c2eac02ef40fb923b5ee5f74e919065f8a4ac Reviewed-on: http://git.am.freescale.net:8181/10106 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2013-04-16powerpc/85xx: add P1020RDB-PD platform supportJerry Huang
The p1020rdb-pd has the similar feature as the p1020rdb. Therefore, p1020rdb-pd use the same platform file as the p1/p2 rdb board. Overview of P1020RDB-PD platform: - DDR3 2GB - NOR flash 64MB - NAND flash 128MB - SPI flash 16MB - I2C EEPROM 256Kb - eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch - eTSEC2 (SGMII PHY) - eTSEC3 (RGMII PHY) - SDHC - 2 USB ports - 4 TDM ports - PCIe Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Change-Id: Ie5295fe5ba8b4490ab6b4c9a6fb85453da759f9a Reviewed-on: http://git.am.freescale.net:8181/1273 Reviewed-by: Xie Xiaobo-R63061 <X.Xie@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05P1025RDB: Add QE TDM supportJiucheng Xu
The P1025RDB-PC have PMC sockets that support QE-TDM function. The patch enable Quicc Engine and the related signals of QE-TDM. Change-Id: Ia694253a9b16754aed41ae04e7c136905dea69d6 Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/908 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05P1021RDB: Add QE TDM supportJiucheng Xu
The P1021RDB-PC have PMC sockets that support QE-TDM function. The patch enable Quicc Engine and the related signals of QE-TDM. Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Change-Id: Ic1b01085322b92442b4e1b3df928b6247580d889 Reviewed-on: http://git.am.freescale.net:8181/902 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2012-09-12powerpc/fsl-pci: Unify pci/pcie initialization codeJia Hongtao
We unified the Freescale pci/pcie initialization by changing the fsl_pci to a platform driver. In previous PCI code architecture the initialization routine is called at board_setup_arch stage. Now the initialization is done in probe function which is architectural better. Also It's convenient for adding PM support for PCI controller in later patch. Now we registered pci controllers as platform devices. So we combine two initialization code as one platform driver. Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-10powerpc/85xx: Add P1024rdb board supportTang Yuantian
The p1024rdb has the similar feature as the p1020rdb. Therefore, p1024rdb use the same platform file as the p1/p2 rdb board. Overview of P2020RDB platform - DDR3 1G - NOR flash 16M - 3 Ethernet interfaces - NAND Flash 32M - SPI EEPROM 16M - SD/MMC - 2 USB ports - 4 TDM ports Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-04-02Merge remote-tracking branch 'kumar/next' into mergeBenjamin Herrenschmidt
2012-03-29powerpc/8xxx: remove 85xx/86xx restrictions from fsl_guts.hTimur Tabi
Remove the check for CONFIG_PPC_85xx and CONFIG_PPC_86xx from fsl_guts.h. The check was originally intended to allow the same header file to be used on 85xx and 86xx systems, even though the Global Utilities register could be different. It turns out that they're not actually different, and so the check is not necessary. In addition, neither macro is defined for 64-bit e5500 kernels, so that causes a build break. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-28Disintegrate asm/system.h for PowerPCDavid Howells
Disintegrate asm/system.h for PowerPC. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> cc: linuxppc-dev@lists.ozlabs.org
2012-03-16powerpc/85xx: Add Quicc Engine support for p1025rdbZhicheng Fan
Signed-off-by: Zhicheng Fan <b32736@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Add p1020rdb-pc platform supportZhicheng Fan
Signed-off-by: Zhicheng Fan <b32736@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: add P1020UTM-PC platform supportJerry Huang
The p1020utm-pc has the similar feature as the p1020rdb. Therefore, p1020utm-pc use the same platform file as the p1/p2 rdb board. Overview of P1020UTM-PC platform: - DDR3 1GB - NOR flash 32MB - I2C EEPROM 256Kb - eTSEC1 (RGMII PHY Atheros AR8021) - eTSEC2 (SGMII PHY Vitesse VSC8221) - eTSEC3 (RGMII PHY Atheros AR8021) - SDHC - 2 USB ports - PCIe (Lane1 to dual SATA controller) Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: add P1020MBG-PC platform supportJerry Huang
The p1020mbg-pc has the similar feature as the p1020rdb. Therefore, p1020mbg-pc use the same platform file as the p1/p2 rdb board. Overview of P1020MBG-PC platform: - DDR3 2GB - NOR flash 64MB - I2C EEPROM 256Kb - eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch - eTSEC2 (SGMII PHY) - eTSEC3 (RGMII PHY) - SDHC - 2 USB ports - 4 TDM ports - PCIe (Lane1 to dual SATA controller) Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Add p1025rdb platform supportZhicheng Fan
Signed-off-by: Zhicheng Fan <b32736@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Adds Support for P2020RDB-PC boardTang Yuantian
P2020RDB-PC Board shares the same design(PCB) as P102x RDB style platforms. The difference between this platform and the already existing P2020RDB is mainly with respect to DDR. The P2020RDB-PC has a DDR3 memory. The P2020RDB-PC also has a CPLD device connected to local bus. The main differences from the P102x RDB-PC is 64-bit DDR and SYSCLK of 100Mhz. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-16powerpc/85xx: Added P1021RDB-PC Platform supportXu Jiucheng
Signed-off-by: Xu Jiucheng <B37781@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-02-22powerpc/mpic: Remove duplicate MPIC_WANTS_RESET flagKyle Moffett
There are two separate flags controlling whether or not the MPIC is reset during initialization, which is completely unnecessary, and only one of them can be specified in the device tree. Also, most platforms in-tree right now do actually want to reset the MPIC during initialization anyways, which means lots of duplicate code passing the MPIC_WANTS_RESET flag. Fix all of the callers which currently do not pass the MPIC_WANTS_RESET flag to pass the MPIC_NO_RESET flag, then remove the MPIC_WANTS_RESET flag and make the code reset the MPIC by default. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-02-22powerpc/mpic: Remove MPIC_BROKEN_FRR_NIRQS and duplicate irq_countKyle Moffett
The mpic->irq_count variable is only used as a software error-checking limit to determine whether or not an IRQ number is valid. In board code which does not manually specify an IRQ count to mpic_alloc(), i.e. 0, it is automatically detected from the number of ISUs and the ISU size. In practice, all hardware ends up with irq_count == num_sources, so all of the runtime checks on mpic->irq_count should just check the value of mpic->num_sources instead. When platform hardware does not correctly report the number of IRQs, which only happens on the MPC85xx/MPC86xx, the MPIC_BROKEN_FRR_NIRQS flag is used to override the detected value of num_sources with the manual irq_count parameter. Since there's no need to manually specify the number of IRQs except in this case, the extra flag can be eliminated and the test changed to "irq_count != 0". Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-07powerpc/mpic: Invert the meaning of MPIC_PRIMARYKyle Moffett
It turns out that there are only 2 in-tree platforms which use MPICs which are not "primary": IBM Cell and PowerMac. To reduce the complexity of the typical board setup code, invert the MPIC_PRIMARY bit into MPIC_SECONDARY. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-07powerpc/mpic: Search for open-pic device-tree node if NULLKyle Moffett
Almost all PowerPC platforms use a standard "open-pic" device node so the mpic_alloc() function now accepts NULL for the device-node. This will cause it to perform a default search with of_find_matching_node(). Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-07powerpc: Consolidate mpic_alloc() OF address translationKyle Moffett
Instead of using the open-coded "reg" property lookup and address translation in mpic_alloc(), directly call of_address_to_resource(). This includes various workarounds for special cases which the naive of_address_translate() does not. Afterwards it is possible to remove the copiously copy-pasted calls to of_address_translate() from the 85xx/86xx/powermac platforms. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-12-07powerpc/85xx: Move mpc85xx_smp_init() decl to a new "smp.h"Kyle Moffett
This removes a bunch of "extern" declarations and CONFIG_SMP ifdefs. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-11-24powerpc/85xx: consolidate of_platform_bus_probe callsDmitry Eremin-Solenikov
85xx board files have a lot of duplication in *_publish_devices()/ *_declare_of_platform_devices() functions. Merge that into a single function common to most of the boards. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-24powerpc/85xx: separate cpm2 pic initDmitry Eremin-Solenikov
Separate handling of CPM2 PIC initialization to mpc85xx_cpm2_pic_init() function. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-22powerpc/85xx: fix mpic configuration in CAMP modeFabio Baltieri
Change the string to check for CAMP mode boot on MPC85xx (eg. P2020) to match the one in the corresponding dts files (p2020rdb_camp_core{0,1}.dts). Without this fix the mpic is configured as in the SMP boot mode, which causes the first core to report a protected source interrupt error for devices of the other core and lock up. Also add MPIC_SINGLE_DEST_CPU on both P2020 based architectures in CAMP mode as suggested by Scott Wood. Thanks. Cc: Scott Wood <scottwood@freescale.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-12powerpc/85xx: Added P1020RDB Platform support.Poonam Aggrwal
P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-12powerpc/85xx: Create dts for each core in CAMP mode for P2020RDBPoonam Aggrwal
This patch creates the dts files for each core and splits the devices between the two cores for P2020RDB. core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto, global-util, pci0, core1 has L2, dma2, eth0, pci1, msi. MPIC is shared between two cores but each core will protect its interrupts from other core by using "protected-sources" of mpic. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-25powerpc/85xx: Add support for P2020RDB boardPoonam Aggrwal
Add support for the P2020RDB reference board from Freescale. Overview of P2020RDB platform - DDR DDR2 1G - NOR Flash 16MByte - NAND Flash 32MByte - 3 Ethernet interfaces 1) etSEC1 - RGMII - connected to a 5 port Vitesse Switch(VSC7385) - Switch is memory mapped through eLBC interface(CS#2) - IRQ1 2) etSEC2 - SGMII - connected to VSC8221 - IRQ2 3) etSEC3 - RGMII - connected to VSC8641 - IRQ3 - 2 1X PCIe interfaces - SD/MMC ,USB - SPI EEPROM - Serial I2C EEPROM Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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