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path: root/arch/powerpc/platforms/85xx/twr_p102x.c
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2014-12-11qe: move qe from arch/powerpc/sysdev/ to drivers/soc/Zhao Qiang
ls1 has qe ip block too, so move qe code from platform directory to public directory. Signed-off-by: Zhao Qiang <B45475@freescale.com> --- patch on upstream can be found with this link: http://patchwork.ozlabs.org/patch/385724/, it is under discussion Change-Id: I39aed531a4792990e3bb8ecc6f4e57f8d9b41bae Reviewed-on: http://git.am.freescale.net:8181/15818 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-05-21powerpc/85xx: p1025twr: add module conditional to fix QE-uart issueXie Xiaobo
A ioport setting was needed when used the QE uart function on TWR-P1025. Added a conditional definition to avoid missing this setting when the QE-uart driver was bulit to a module. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Change-Id: I95b40c760335ce5fa7a27a94287dbef28219b5fa Reviewed-on: http://git.am.freescale.net:8181/6643 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Thomas Trefny <Tom.Trefny@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/12045 Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2013-05-28powerpc/85xx: Disable CTS pin for QE UART0Xie Xiaobo
On P1025TWR board, the UCC7 acted as UART port0. However, The UCC7's CTS pin is low level in default, it will impact the transmission in full duplex communication. So disable the Flow control pin - CTS. The UCC7 UART just can use RXD and TXD pins. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Change-Id: I8ab9b3edb0edb6440ce32a83fbcf0200c8eb54f7 Reviewed-on: http://git.am.freescale.net:8181/2706 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-25powerpc/85xx: Add TWR-P1025 board supportXie Xiaobo
TWR-P1025 Overview ----------------- 512Mbyte DDR3 (on board DDR) 64MB Nor Flash eTSEC1: Connected to RGMII PHY AR8035 eTSEC3: Connected to RGMII PHY AR8035 Two USB2.0 Type A One microSD Card slot One mini-PCIe slot One mini-USB TypeB dual UART Change-Id: I30d2b481ecba3d67f9484a5194a9278be34d44a4 Signed-off-by: Michael Johnston <michael.johnston@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/1153 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>