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AgeCommit message (Expand)Author
2006-03-20[SPARC64]: More SUN4V PCI controller work.David S. Miller
2006-03-20[SPARC64]: Beginnings of SUN4V PCI controller support.David S. Miller
2006-03-20[SPARC64]: Fetch cpu mid properly on sun4v.David S. Miller
2006-03-20[SPARC64]: SUN4V memory exception trap handlers.David S. Miller
2006-03-20[SPARC64]: Hypervisor TSB context switching.David S. Miller
2006-03-20[SPARC64]: Implement sun4v TSB miss handlers.David S. Miller
2006-03-20[SPARC64]: kernel/cpu.c needs asm/spitfire.hDavid S. Miller
2006-03-20[SPARC64]: Print ARCH as SUN4V when tlb_type is hypervisor.David S. Miller
2006-03-20[SPARC64]: Detect sun4v early in boot process.David S. Miller
2006-03-20[SPARC64]: Sun4v cross-call sending support.David S. Miller
2006-03-20[SPARC64]: Sun4v interrupt handling.David S. Miller
2006-03-20[SPARC64]: Allocate and register the 4 sun4v mondo queues at bootup.David S. Miller
2006-03-20[SPARC64]: Verify all trap_per_cpu assembler offsets in trap_init()David S. Miller
2006-03-20[SPARC64]: Patch up mmu context register writes for sun4v.David S. Miller
2006-03-20[SPARC64]: Register per-cpu fault status area with sun4v hypervisor.David S. Miller
2006-03-20[SPARC64]: Niagara copy/clear page.David S. Miller
2006-03-20[SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patchDavid S. Miller
2006-03-20[SPARC64]: Initial sun4v TLB miss handling infrastructure.David S. Miller
2006-03-20[SPARC64]: Add missing memory barriers to instruction patching functions.David S. Miller
2006-03-20[SPARC64]: Sanitize %pstate writes for sun4v.David S. Miller
2006-03-20[SPARC64]: Kill all %pstate changes in context switch code.David S. Miller
2006-03-20[SPARC64]: Add initial code to twiddle %gl on trap entry/exit.David S. Miller
2006-03-20[SPARC64]: Fill dead cycles on trap entry with real work.David S. Miller
2006-03-20[SPARC64]: Add sun4v case to __GET_CPUID() patch tables.David S. Miller
2006-03-20[SPARC64]: Niagara optimized memcpy() and copy_{to,from}_user().David S. Miller
2006-03-20[SPARC64]: Add some hypervisor tlb_type checks.David S. Miller
2006-03-20[SPARC64]: SUN4V hypervisor TLB flush support code.David S. Miller
2006-03-20[SPARC64]: Refine register window trap handling.David S. Miller
2006-03-20[SPARC64]: Add explicit register args to trap state loading macros.David S. Miller
2006-03-20[SPARC64]: Refine code sequences to get the cpu id.David S. Miller
2006-03-20[SPARC64]: Turn off TSB growing for now.David S. Miller
2006-03-20[SPARC64]: Correctable ECC errors cannot occur at trap level > 0.David S. Miller
2006-03-20[SPARC64]: Access TSB with physical addresses when possible.David S. Miller
2006-03-20[SPARC64]: Don't clobber alt-global %g4 on window fixups.David S. Miller
2006-03-20[SPARC64]: Fix race in LOAD_PER_CPU_BASE()David S. Miller
2006-03-20[SPARC64]: Kill swapper_pgd_zero, totally unused.David S. Miller
2006-03-20[SPARC64]: Fix too early reference to %g6David S. Miller
2006-03-20[SPARC64]: Kill hard-coded %pstate setting in sparc_exit.David S. Miller
2006-03-20[SPARC64]: Increase swapper_tsb size to 32K.David S. Miller
2006-03-20[SPARC64]: Kill sole argument passed to setup_tba().David S. Miller
2006-03-20[SPARC64]: Kill PROM locked TLB entry preservation code.David S. Miller
2006-03-20[SPARC64]: Use sparc64_highest_unlocked_tlb_ent in __tsb_context_switch()David S. Miller
2006-03-20[SPARC64]: Fix bogus flush instruction usage.David S. Miller
2006-03-20[SPARC64]: Fix incorrect TSB lock bit handling.David S. Miller
2006-03-20[SPARC64]: Kill {save,restore}_alternate_globals()David S. Miller
2006-03-20[SPARC64]: Preload TSB entries from update_mmu_cache().David S. Miller
2006-03-20[SPARC64]: Dynamically grow TSB in response to RSS growth.David S. Miller
2006-03-20[SPARC64]: Add infrastructure for dynamic TSB sizing.David S. Miller
2006-03-20[SPARC64]: TSB refinements.David S. Miller
2006-03-20[SPARC64]: Elminate all usage of hard-coded trap globals.David S. Miller
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