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2014-12-11rheap: move rheap.c from arch/powerpc/lib/ to lib/Zhao Qiang
qe need to use the rheap, so move it to public directory. Signed-off-by: Zhao Qiang <B45475@freescale.com> --- upstream link: http://patchwork.ozlabs.org/patch/393170/ it is under discussion. Change-Id: Ied2765d6e0eb3b7ade0fef02cfe226c8a8566c5f Reviewed-on: http://git.am.freescale.net:8181/16841 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11qe_common: add qe common functions to qe_common.cZhao Qiang
qe need to call some common functions, move them into public directory, add a new file drivers/soc/qe/qe_common.c for them. Signed-off-by: Zhao Qiang <B45475@freescale.com> --- upstream link: http://patchwork.ozlabs.org/patch/393169/ it is under discussion. Change-Id: Ib2b252f355921291b596d8ddc6bbe17aa53384b2 Reviewed-on: http://git.am.freescale.net:8181/16840 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11qe: move qe from arch/powerpc/sysdev/ to drivers/soc/Zhao Qiang
ls1 has qe ip block too, so move qe code from platform directory to public directory. Signed-off-by: Zhao Qiang <B45475@freescale.com> --- patch on upstream can be found with this link: http://patchwork.ozlabs.org/patch/385724/, it is under discussion Change-Id: I39aed531a4792990e3bb8ecc6f4e57f8d9b41bae Reviewed-on: http://git.am.freescale.net:8181/15818 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi-nor:fsl-quadspi:Add LS1021 support for fsl_quadspiChao Fu
FSL Quadspi module register bitwise is big-endian, but on ohter paltform is little endian. Add functions for Quadspi register read/write for bitwise: qspi_readl qpsi_writel Add devtype for LS1021: struct fsl_qspi_devtype_data ls1_data Signed-off-by: Chao Fu <B44548@freescale.com> The upstream status of this patch can be found at: http://patchwork.ozlabs.org/patch/399388/ Change-Id: Ib1a8bc11a52e8d9bb1021c8956a5783d3915de2e Reviewed-on: http://git.am.freescale.net:8181/20296 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi:fsl-dspi:add dspi tcfq mode transfer supportChao Fu
TCFQ is interrupt of Transfer Complete Flag in DSPI module. EOQ is interrupt of End of Queue Flag in DSPI module. For adopting of different platform, either of them is a way of DSPI transfer data. This patch add TCF support for DSPI module in other platform. The software will be changed in two transfer methods as followwing: EOQ TCFQ transfer data: dspi_eoq_write dspi_tcfq_write receive data: dspi_eoq_read dspi_tcfq_read Using which method will decided by paltform soc dtsi file. Remove bitbang: Add tcf funtions, DSPI module need get cs change information in a spi transfer. According cs change, DSPI will give last data the right flag. Bitbang provide cs change behind the last data in a transfer. So DSPI can not deal the last data in every transfer properly, so remove the bitbang in the driver. Merge duplicate code: dspi_data_from_popr dspi_data_to_pushr Remove clk reference in regmap I/O: Set the clk parament is NULL in devm_regmap_init_mmio_clk, it will avoid clk handle in every register read/write, and advance tranferring efficiency. Signed-off-by: Chao Fu <b44548@freescale.com> The upstream status of this patch can be found at: https://patchwork.kernel.org/patch/4974181 Change-Id: I0ed6c1598c111e74b5e53c248e00dec2398fa900 Reviewed-on: http://git.am.freescale.net:8181/20096 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11drivers/rtc/rtc-ds3232.c: enable ds3232 to work as wakeup sourceXiubo Li
Add suspend/resume and device_init_wakeup to enable ds3232 as wakeup source, /sys/class/rtc/rtcX/wakealarm for set wakeup alarm. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> --- This patch is pulled back from upstream with few backport changes: commit c93a3ae2d213ff75a279fe6e28d8f41ca7f01483 Change-Id: I63ec38f3757becb1a2c37d07e5d03de38ac7e996 Reviewed-on: http://git.am.freescale.net:8181/21139 Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi: fsl-dspi: Convert to use regmap framework's endianness method.Xiubo Li
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Acked-by: Chao Fu <b44548@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit c99428d035908b9c0b8be452f9b091bc5e090256) Change-Id: I4afafcd1d5fd244ea287f899bca03baa95c61531 Reviewed-on: http://git.am.freescale.net:8181/20091 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi: fsl-dspi: Make of_device_id array constJingoo Han
Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 790d190257b339bba9ff821d7d49f4567146f4ad) Change-Id: I27ecbe600bf91f328e2762cb65dfe76261060489 Reviewed-on: http://git.am.freescale.net:8181/20090 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi: fsl-dspi: Fix memory leakAxel Lin
The memory allocated for chip is not freed anywhere. Convert to use devm_kzalloc to fix the memory leak. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 0e0cd9ea8961b82947a40471080e7968b634820e) Change-Id: Ia54f0ab47d9e36a375f66ea4c285b2f4ecc09ed4 Reviewed-on: http://git.am.freescale.net:8181/20089 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi: fsl-dspi: Use SIMPLE_DEV_PM_OPS macroJingoo Han
Use SIMPLE_DEV_PM_OPS macro in order to make the code simpler. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit ba811addff3d29d1ea9861dbfc06e8ef80714f94) Change-Id: Ic2086e577d7d11df710c03c85202864b76151882 Reviewed-on: http://git.am.freescale.net:8181/20088 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi/fsl-dspi: Remove some coding sytle not in standardChao Fu
Remove some coding sytle not in standard in former code. Signed-off-by: Chao Fu <b44548@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 88386e858bbb21eb05c15c040dbb3e6ad1cb3568) Change-Id: Ia4d6096ca86bf5e939748017120ddf33dafdb12e Reviewed-on: http://git.am.freescale.net:8181/20087 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi/fsl-dspi: Convert to use regmap and add big-endian supportChao Fu
Freescale DSPI module will have two endianess in different platform, but ARM is little endian. So when DSPI in big endian, core in little endian, readl and writel can not adjust R/W register in this condition. This patch will remove general readl/writel, and import regmap mechanism. Data endian will be transfered in regmap APIs. Documents: dspi add bool "big-endian" in dts node if DSPI module work in big endian. Signed-off-by: Chao Fu <b44548@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 1acbdeb92c87fc18eade0815dedc257fe45b88b7) Change-Id: I60e630bb18a2101af3154633bbe5824a52ac45f2 Reviewed-on: http://git.am.freescale.net:8181/20086 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi: Remove duplicate code to set default bits_per_word settingChao Fu
The implementation in spi_setup() already set spi->bits_per_word = 8 when spi->bits_per_word is 0 before calling spi->master->setup. So we don't need to do it again in setup() callback. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Barry Song <Baohua.Song@csr.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 23061f1eb844edd349c3a0f5f40e244c9d2abfde) Change-Id: I842867bbb99dd71bfcf30ac90300c6ca23c384b9 Reviewed-on: http://git.am.freescale.net:8181/20085 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi: fsl-dspi: Add missing breaks for switch casesAxel Lin
Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit e07725be735e1791cf74e9db06a8bde62e1f517d) Change-Id: Id0205a7e671df191a232d328091f1dc8a963b9f1 Reviewed-on: http://git.am.freescale.net:8181/20084 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi: fsl-dspi: add missing clk_disable_unprepare() in dspi_remove()Wei Yongjun
clock source is prepared and enabled by clk_prepare_enable() in probe function, but no disable or unprepare in remove. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 05209f457069e595ce0262a9032cbade05398571) Change-Id: Ib45ea4b0fb7f211e5e31352268c4aff4afd4b3e3 Reviewed-on: http://git.am.freescale.net:8181/20083 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi: bitbang: Let spi_bitbang_start() take a reference to masterAxel Lin
Many drivers that use bitbang library have a leak on probe error paths. This is because once a spi_master_get() call succeeds, we need an additional spi_master_put() call to free the memory. Fix this issue by moving the code taking a reference to master to spi_bitbang_start(), so spi_bitbang_start() will take a reference to master on success. With this change, the caller is responsible for calling spi_bitbang_stop() to decrement the reference and spi_master_put() as counterpart of spi_alloc_master() to prevent a memory leak. So now we have below patten for drivers using bitbang library: probe: spi_alloc_master -> Init reference count to 1 spi_bitbang_start -> Increment reference count remove: spi_bitbang_stop -> Decrement reference count spi_master_put -> Decrement reference count (reference count reaches 0) Fixup all users accordingly. Signed-off-by: Axel Lin <axel.lin@ingics.com> Suggested-by: Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> Acked-by: Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 94c69f765f1b4a658d96905ec59928e3e3e07e6a) Change-Id: Ifce35be3f5b3a64cfbf8f42dcafa35134f039899 Reviewed-on: http://git.am.freescale.net:8181/20082 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi: fsl-dspi: several minor improvements and fixesUwe Kleine-König
- improve dependencies using COMPILE_TEST - fix a typo - drop platform_set_drvdata(pdev, NULL) in error path of probe - make MODULE_LICENSE match the header Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit b444d1dfe296433a93d6b814d924e0ab99ad7e7b) Change-Id: Id41bb981d35f216297d5cc49c071a64c99912c5b Reviewed-on: http://git.am.freescale.net:8181/20081 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi: fsl-dspi: add missing __iomem annotationJingoo Han
Added missing __iomem annotation in order to fix the following sparse warnings: drivers/spi/spi-fsl-dspi.c:140:16: warning: incorrect type in argument 1 (different address spaces) drivers/spi/spi-fsl-dspi.c:140:16: expected void const volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:140:16: got void * drivers/spi/spi-fsl-dspi.c:143:9: warning: incorrect type in argument 2 (different address spaces) drivers/spi/spi-fsl-dspi.c:143:9: expected void volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:143:9: got void * drivers/spi/spi-fsl-dspi.c:132:18: warning: incorrect type in argument 1 (different address spaces) drivers/spi/spi-fsl-dspi.c:132:18: expected void const volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:132:18: got void * drivers/spi/spi-fsl-dspi.c:241:17: warning: incorrect type in argument 2 (different address spaces) drivers/spi/spi-fsl-dspi.c:241:17: expected void volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:241:17: got void * drivers/spi/spi-fsl-dspi.c:132:18: warning: incorrect type in argument 1 (different address spaces) drivers/spi/spi-fsl-dspi.c:132:18: expected void const volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:132:18: got void * drivers/spi/spi-fsl-dspi.c:259:29: warning: incorrect type in argument 1 (different address spaces) drivers/spi/spi-fsl-dspi.c:259:29: expected void const volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:259:29: got void * drivers/spi/spi-fsl-dspi.c:266:29: warning: incorrect type in argument 1 (different address spaces) drivers/spi/spi-fsl-dspi.c:266:29: expected void const volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:266:29: got void * drivers/spi/spi-fsl-dspi.c:298:9: warning: incorrect type in argument 2 (different address spaces) drivers/spi/spi-fsl-dspi.c:298:9: expected void volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:298:9: got void * drivers/spi/spi-fsl-dspi.c:299:9: warning: incorrect type in argument 2 (different address spaces) drivers/spi/spi-fsl-dspi.c:299:9: expected void volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:299:9: got void * drivers/spi/spi-fsl-dspi.c:300:9: warning: incorrect type in argument 2 (different address spaces) drivers/spi/spi-fsl-dspi.c:300:9: expected void volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:300:9: got void * drivers/spi/spi-fsl-dspi.c:303:17: warning: incorrect type in argument 2 (different address spaces) drivers/spi/spi-fsl-dspi.c:303:17: expected void volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:303:17: got void * drivers/spi/spi-fsl-dspi.c:318:21: warning: incorrect type in argument 1 (different address spaces) drivers/spi/spi-fsl-dspi.c:318:21: expected void const volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:318:21: got void * drivers/spi/spi-fsl-dspi.c:327:9: warning: incorrect type in argument 2 (different address spaces) drivers/spi/spi-fsl-dspi.c:327:9: expected void volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:327:9: got void * drivers/spi/spi-fsl-dspi.c:386:9: warning: incorrect type in argument 2 (different address spaces) drivers/spi/spi-fsl-dspi.c:386:9: expected void volatile [noderef] <asn:2>*addr drivers/spi/spi-fsl-dspi.c:386:9: got void * drivers/spi/spi-fsl-dspi.c:485:20: warning: incorrect type in assignment (different address spaces) drivers/spi/spi-fsl-dspi.c:485:20: expected void *base drivers/spi/spi-fsl-dspi.c:485:20: got void [noderef] <asn:2>* Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 2ef3599d8181afcbd347226faba75991f9e008fc) Change-Id: I51696586aa10ad6f848614146baed2f64dd5ff9a Reviewed-on: http://git.am.freescale.net:8181/20080 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: spi-nor: read 6 bytes for the IDChao Fu
Currently, we read 5 bytes for ID, but s25fl128s has the same ext_id(0x4d01) with s25fl129p1. The s25fl128s can support the DDR Quad read, while s25fl129p1 does not. So we have to distinguish the two NOR flashs. This patch reads out 6 bytes for the ID, and use the 6 bytes ID to search the right flash_info. The detail of the patch is: [1] change the "ext_id" from u16 to u32. We can store two bytes or three bytes with the @ext_id now. [2] search the right flash_info with the 6byte ID and the new @ext_id. We use "matched" variable to track the legacy two bytes @ext_id. If the flash_info's @ext_id is three bytes, we will use the sixth byte of the ID to check it. [3] add the new item to spi_nor_ids for s25fl128s. Signed-off-by: Huang Shijie <b32955@freescale.com> The upstream link of this patch: http://patchwork.ozlabs.org/patch/353244/ Change-Id: Id27774eefbf9e1a8f80e1dcd8fb0d3f9363923c1 Reviewed-on: http://git.am.freescale.net:8181/20134 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: fsl-quadspi: add DDR quad read support for MicronChao Fu
Add DDR quad read opcode and LUT sequence for Micron N25Q256A. The performace : ================================================= mtd_speedtest: MTD device: 1 mtd_speedtest: not NAND flash, assume page size is 512 bytes. mtd_speedtest: MTD device size 33554432, eraseblock size 65536, page size 512, count of eraseblocks 512, pages per eraseblock 128, OOB size 0 mtd_speedtest: testing eraseblock write speed mtd_speedtest: eraseblock write speed is 2426 KiB/s mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 32157 KiB/s mtd_speedtest: testing page write speed mtd_speedtest: page write speed is 2362 KiB/s mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 17741 KiB/s mtd_speedtest: testing 2 page write speed mtd_speedtest: 2 page write speed is 2384 KiB/s mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 24058 KiB/s mtd_speedtest: Testing erase speed mtd_speedtest: erase speed is 1927529 KiB/s mtd_speedtest: Testing 2x multi-block erase speed mtd_speedtest: 2x multi-block erase speed is 2184533 KiB/s mtd_speedtest: Testing 4x multi-block erase speed mtd_speedtest: 4x multi-block erase speed is 2184533 KiB/s mtd_speedtest: Testing 8x multi-block erase speed mtd_speedtest: 8x multi-block erase speed is 2340571 KiB/s mtd_speedtest: Testing 16x multi-block erase speed mtd_speedtest: 16x multi-block erase speed is 2340571 KiB/s mtd_speedtest: Testing 32x multi-block erase speed mtd_speedtest: 32x multi-block erase speed is 2340571 KiB/s mtd_speedtest: Testing 64x multi-block erase speed mtd_speedtest: 64x multi-block erase speed is 2340571 KiB/s mtd_speedtest: finished ================================================= Signed-off-by: Huang Shijie <b32955@freescale.com> The upstream link of this patch: https://patchwork.kernel.org/patch/4075001/ Change-Id: Ice094cec23114af5cda5dd4b24c3b2e60719fd6a Reviewed-on: http://git.am.freescale.net:8181/20132 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: spi-nor: add DDR quad read support for MicronChao Fu
This patch adds the DDR(or DTR) quad read support for the Micron SPI NOR flash. Tested with n25q256a. Signed-off-by: Huang Shijie <b32955@freescale.com> The upstream link of this patch: https://patchwork.kernel.org/patch/4075011/ Change-Id: Ib226886ff8d9e80d6aa5fb72dc86278188b2e3a3 Reviewed-on: http://git.am.freescale.net:8181/20131 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: fsl-quadspi: add the DDR quad read support for Spansion NORChao Fu
Add the DDR quad read support for the fsl-quadspi driver. Check the "spi-nor,ddr-quad-read-dummy" DT property, if the DT node is exit, it means we could enable the DDR quad read. (1) Test this patch with imx6sx-sdb board (Spansion s25fl128s) The clock rate is 66MHz. (2) The information of NOR flash: ----------------------------------------------- root@imx6qdlsolo:~# mtdinfo /dev/mtd0 mtd0 Name: 21e4000.qspi Type: nor Eraseblock size: 65536 bytes, 64.0 KiB Amount of eraseblocks: 256 (16777216 bytes, 16.0 MiB) Minimum input/output unit size: 1 byte Sub-page size: 1 byte Character device major/minor: 90:0 Bad blocks are allowed: false Device is writable: true ----------------------------------------------- (3) Test this patch set with UBIFS & bonnie++: ----------------------------------------------- ubiattach /dev/ubi_ctrl -m 0 ubimkvol /dev/ubi0 -N test -m mount -t ubifs ubi0:test tmp bonnie++ -d tmp -u 0 -s 10 -r 5 ----------------------------------------------- (4) Test this patch with mtd_speedtest.ko root@imx6qdlsolo:~# insmod mtd_speedtest.ko dev=0 ================================================= mtd_speedtest: MTD device: 0 mtd_speedtest: not NAND flash, assume page size is 512 bytes. mtd_speedtest: MTD device size 16777216, eraseblock size 65536, page size 512, count of eraseblocks 256, pages per eraseblock 128, OOB size 0 mtd_speedtest: testing eraseblock write speed mtd_speedtest: eraseblock write speed is 665 KiB/s mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 49799 KiB/s mtd_speedtest: testing page write speed mtd_speedtest: page write speed is 662 KiB/s mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 24236 KiB/s mtd_speedtest: testing 2 page write speed mtd_speedtest: 2 page write speed is 657 KiB/s mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 32637 KiB/s mtd_speedtest: Testing erase speed mtd_speedtest: erase speed is 518 KiB/s mtd_speedtest: Testing 2x multi-block erase speed mtd_speedtest: 2x multi-block erase speed is 506 KiB/s mtd_speedtest: Testing 4x multi-block erase speed mtd_speedtest: 4x multi-block erase speed is 503 KiB/s mtd_speedtest: Testing 8x multi-block erase speed mtd_speedtest: 8x multi-block erase speed is 501 KiB/s mtd_speedtest: Testing 16x multi-block erase speed mtd_speedtest: 16x multi-block erase speed is 498 KiB/s mtd_speedtest: Testing 32x multi-block erase speed mtd_speedtest: 32x multi-block erase speed is 496 KiB/s mtd_speedtest: Testing 64x multi-block erase speed mtd_speedtest: 64x multi-block erase speed is 495 KiB/s mtd_speedtest: finished ================================================= (5) Conclusion: The DDR quad read could be 49799 KiB/s. Signed-off-by: Huang Shijie <b32955@freescale.com> The upstream status of this patch can be found at: https://patchwork.kernel.org/patch/4074991/ Change-Id: I80c58bec32659d375c4656402e0c3d3ce3ba2e55 Reviewed-on: http://git.am.freescale.net:8181/20130 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: fsl-quadspi: use the information stored in spi-nor{}Chao Fu
We can get the read/write/erase opcode from the spi nor framework now. What's more is that we can get the correct dummy cycles. This patch uses the information stored in the spi_nor{} to remove the hardcode in the fsl_qspi_init_lut(). Signed-off-by: Huang Shijie <b32955@freescale.com> The upstream status of this patch can be found: https://patchwork.kernel.org/patch/4074971/ Change-Id: I32f982872df1729582f4122ac0dede934d749a04 Reviewed-on: http://git.am.freescale.net:8181/20129 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: spi-nor: add DDR quad read supportChao Fu
This patch adds the DDR quad read support by the following: [1] add SPI_NOR_DDR_QUAD read mode. [2] add DDR Quad read opcodes: SPINOR_OP_READ_1_4_4_D / SPINOR_OP_READ4_1_4_4_D [3] add set_ddr_quad_mode() to initialize for the DDR quad read. Currently it only works for Spansion NOR. [3] about the dummy cycles. We set the dummy with 8 for DDR quad read by default. The m25p80.c can not support the DDR quad read, but the SPI NOR controller can set the dummy value in its child DT node, and the SPI NOR framework can parse it out. Test this patch for Spansion s25fl128s NOR flash. Signed-off-by: Huang Shijie <b32955@freescale.com> The upstream status of this patch can be found at: https://patchwork.kernel.org/patch/4074961 Change-Id: Id67e247e357bdd8bea99816e31f603898671d968 Reviewed-on: http://git.am.freescale.net:8181/20125 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: spi-nor: unify read opcode variants with ST SPI FSMBrian Norris
serial_flash_cmds.h defines our opcodes a little differently. Let's borrow its naming, since it's borrowed from the SFDP standard, and it's more extensible. This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode listing. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com> (cherry picked from commit 58b89a1f4c2a65b10b8f7b90b6ff2161b19bb0d1) Change-Id: Id3eff06b36acaa388d2581af59abc569c6a7f474 Reviewed-on: http://git.am.freescale.net:8181/20058 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: spi-nor: add a new field for spi_nor{}Chao Fu
We need the SPI NOR child node to store some specific features, such as the dummy cycles for the DDR Quad read. But now, we only have the @dev field in the spi_nor{}. The @dev may points to a spi_device{} for m25p80, while it may points to a platform_deivice{} for the SPI NOR controller, such as fsl_quadspi.c. It is not convenient for us to get come information from the SPI NOR flash. This patch adds a new field @np to spi_nor{}, it points to the child node for the SPI NOR flash. Signed-off-by: Huang Shijie <b32955@freescale.com> The patch was pending at: https://patchwork.kernel.org/patch/4074931/ Change-Id: I0613744ca972ddc7481d82488d3e4c4e74c67652 Reviewed-on: http://git.am.freescale.net:8181/20057 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: spi-nor: fix the wrong dummy valueChao Fu
For the DDR Quad read, the dummy cycles maybe 3 or 6 which is less then 8. The dummy cycles is actually 8 for SPI fast/dual/quad read. This patch makes preparations for the DDR quad read, it fixes the wrong dummy value for both the spi-nor.c and m25p80.c. Signed-off-by: Huang Shijie <b32955@freescale.com> The upstream status of this patch can be found at: https://patchwork.kernel.org/patch/4074921/ Change-Id: I7ca208d1964812f77f66708c659d826c39baff4d Reviewed-on: http://git.am.freescale.net:8181/20056 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: Revive dual read supportGeert Uytterhoeven
Commit 03e296f613affcc2671c1e86d8c25ecad867204e ("mtd: m25p80: use the SPI nor framework") accidentally removed support for Dual SPI read transfers. Add it back. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit 8848e161b79421e340bb13facc11d89570b77940) Change-Id: Ia4651487c4ca9f76063c7ec2bb8e04644e21b1df Reviewed-on: http://git.am.freescale.net:8181/20055 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_*Brian Norris
Qualify these with a better namespace, and prepare them for use in more drivers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com> (cherry picked from commit b02e7f3ef0beb72da8fc64542f0ac977996ec56b) Change-Id: I50fac2cb23653825b2f8e3ac65dd0ecb35eaf78b Reviewed-on: http://git.am.freescale.net:8181/20054 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: use the SPI nor frameworkBrian Norris
Use the new SPI nor framework, and rewrite the m25p80: (0) remove all the NOR comands. (1) change the m25p->command to an array. (2) implement the necessary hooks, such as m25p80_read/m25p80_write. Tested with the m25p32. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> [Brian: rebased] Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit 03e296f613affcc2671c1e86d8c25ecad867204e) Change-Id: I8ac0159ab3d572cd12bdc1e5b2b6e6c5057b8359 Reviewed-on: http://git.am.freescale.net:8181/20053 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: add Macronix mx66l1g55g 1Gbit SPI flashBrian Norris
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Marek Vasut <marex@denx.de> (cherry picked from commit 6f7db7f3203a0bd48170807adeb53dd401d29110) Change-Id: I84a2d2385c1196c943d9d6558cedded87885e4f8 Reviewed-on: http://git.am.freescale.net:8181/20052 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: add support for the Spansion s25fl008k chipKuninori Morimoto
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit bec44c45c245b38662f1e61bf0bde95fac1e7fb5) Change-Id: Id9363959c57004a211d216c745c9584da8d2cdd0 Reviewed-on: http://git.am.freescale.net:8181/20051 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: Use positive logic to check JEDEC IDAxel Lin
For slightly better readability. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit b2fda1296bb8e213a6bad3937326ae98c4c4773c) Change-Id: Ifadc84eb60ed11bf59c47691cfe58b6a5ecb2274 Reviewed-on: http://git.am.freescale.net:8181/20050 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: delete non-required instances of include <linux/init.h>Chao Fu
None of these files are actually using any __init type directives and hence don't need to include <linux/init.h>. Most are just a left over from __devinit and __cpuinit removal, or simply due to code getting copied from one driver to the next. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: linux-mtd@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> [Brian: dropped one incorrect hunk] Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit 3ea5b037e750274659648b58fb97426566a90373) Change-Id: I9e527be3d3783b665bb659e5e2c977bd4f2b64cc Reviewed-on: http://git.am.freescale.net:8181/20049 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: Enable Dual SPI read transfers for s25fl256s1 and s25fl512sGeert Uytterhoeven
Spansion s25fl256s1 and s25fl512s support Dual SPI transfers, hence set the M25P80_DUAL_READ flag. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit f5e00838e83f6fc93f42c7a01b0c612031955b31) Change-Id: I2e154cafc4e97d1663432bd160d2ec3fc3b98636 Reviewed-on: http://git.am.freescale.net:8181/20048 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: Add dual read supportGeert Uytterhoeven
Add support for Dual SPI read transfers, which is supported by some Spansion SPI FLASHes. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit dbbafb74239e8296bc20f86366b3f38e13650900) Change-Id: Ic69dfc56d0cd556ee00ab2181d4a88709929d56f Reviewed-on: http://git.am.freescale.net:8181/20047 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: Set rx_nbits for Quad SPI transfersGeert Uytterhoeven
When using the Quad Read opcode, SPI masters still use Single SPI transfers, as spi_transfer.rx_nbits defaults to SPI_NBITS_SINGLE. Use SPI_NBITS_QUAD to fix this. While an earlier version of commit 3487a63955c34ea508bcf4ca5131ddd953876e2d ("drivers: mtd: m25p80: add quad read support") did this correctly, it was forgotten in the version that got merged. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit 464e906737d6eba2fe63e913e0df4306423b4f61) Change-Id: Idff0abef064a56cb91958b475359ae0f663efdc0 Reviewed-on: http://git.am.freescale.net:8181/20046 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: Enable Quad SPI read transfers for s25fl512sGeert Uytterhoeven
Spansion s25fl512s supports Quad SPI transfers, hence set the M25P80_QUAD_READ flag. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit d8d5d10d0f27d1975e71617efff941321a0dc142) Change-Id: I85800faa7ea1eff351d5e13f11e2f61ee7bb4380 Reviewed-on: http://git.am.freescale.net:8181/20045 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: assign default read commandBrian Norris
In the following commit (in -next): commit 8552b439aba7f32063755d23f79ca27b4d0a3115 drivers: mtd: m25p80: convert "bool" read check into an enum We converted the boolean 'fast_read' property to become an enum 'flash_read', but at the same time, we changed the conditional path so that it doesn't choose a default value in some cases (technically, we choose the correct default simply by virtue of devm_kzalloc(), which zeroes this out to be a NORMAL read operation, but still...). Fix this by setting a default for the 'else' clause. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Sourav Poddar <sourav.poddar@ti.com> Acked-by: Marek Vasut <marex@denx.de> (cherry picked from commit 99ed1a167578f85963a0cdf5fd7b2291eaecc400) Change-Id: Ic0d5d184ad7cf702a6027271a2a5388b37a1a0ca Reviewed-on: http://git.am.freescale.net:8181/20044 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: Use OPCODE_QUAD_READ_4B for 4-byte addressingGeert Uytterhoeven
commit 3487a63955c34ea508bcf4ca5131ddd953876e2d ("drivers: mtd: m25p80: add quad read support") in -next added both the 3-byte OPCODE_QUAD_READ and the 4-byte OPCODE_QUAD_READ_4B, but incorrectly uses OPCODE_QUAD_READ for both 3-byte and 4-byte addressing. Use OPCODE_QUAD_READ_4B in the 4-byte case to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit 7587f64d546d6a05dab0a7d1ac964e7ac12072f0) Change-Id: I94b049c4e645600e8b692e835f1eb427b1292ab1 Reviewed-on: http://git.am.freescale.net:8181/20043 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: add support for m25px16Igor Grinberg
Add support for Micron m25px16 spi flash chip. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit 574926c5bc3d787bb0b935b99d8825b3199ba76b) Change-Id: Id66a4ca5be6ff4b6ea9debbb0eeba372ceafbb69 Reviewed-on: http://git.am.freescale.net:8181/20042 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11drivers: mtd: m25p80: add quad read supportSourav Poddar
Some flash also support quad read mode. Adding support for quad read mode in m25p80 for Spansion and Macronix flash. [Tweaked by Brian] With this patch, quad-read support will override fast-read and normal-read, if the SPI controller and flash chip both support it. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit 3487a63955c34ea508bcf4ca5131ddd953876e2d) Change-Id: Ib5ea483806cb7237bc23d4219626a198b09aecce Reviewed-on: http://git.am.freescale.net:8181/20041 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11drivers: mtd: m25p80: convert "bool" read check into an enumSourav Poddar
This is a cleanup prior to adding quad read support. This will facilitate easy addition of more read commands check under an enum rather that defining a separate bool for it. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit 8552b439aba7f32063755d23f79ca27b4d0a3115) Change-Id: I9c8d509ef64ff555c22bde09bf13f74b65655f4d Reviewed-on: http://git.am.freescale.net:8181/20040 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: fixup device removal failure pathBrian Norris
Device removal should fail if MTD unregistration fails. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> (cherry picked from commit 9650b9bec61d861b6b59d09eb389410b05d196e4) Change-Id: Ia597ef093f4d1492f9d04c4a7bbaa5be32e5d161 Reviewed-on: http://git.am.freescale.net:8181/20039 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: add support for Macronix mx25l3255eBrian Norris
A new 32Mbit SPI NOR flash from Macronix. Nothing special. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> (cherry picked from commit 5ff14821a37c92d139181c3fbc939afa993b959f) Change-Id: I677b8981e01bbdc7496b86674ab56749959edbeb Reviewed-on: http://git.am.freescale.net:8181/20038 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: remove 'disabled' device checkBrian Norris
It seems like the following commit was never necessary commit 5f949137952020214cd167093dd7be448f21c079 Author: Shaohui Xie <Shaohui.Xie@freescale.com> Date: Fri Oct 14 15:49:00 2011 +0800 mtd: m25p80: don't probe device which has status of 'disabled' because it duplicates the code in of_platform_device_create_pdata() which ensures that 'disabled' nodes are never instantiated. Also, drop the __maybe_unused. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: <devicetree@vger.kernel.org> (cherry picked from commit dc525ff4705cee2291b1637a650489aca86ac937) Change-Id: I01e898a2d0cbf26e144e498eea6b0eec53c5cfdf Reviewed-on: http://git.am.freescale.net:8181/20037 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: re-align ID entriesChao Fu
No change in the table data. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Sourav Poddar <sourav.poddar@ti.com> (cherry picked from commit 6e5d9bda27000c682a9b38f0466941007e295f82) Change-Id: I295d6300994b0a7f852cc4a2dcd3441bf2f813cb Reviewed-on: http://git.am.freescale.net:8181/20035 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11PCI: Layerscape: Add Layerscape PCIe driverMinghuan Lian
Add support for Freescale Layerscape PCIe controller. This driver re-uses the designware core code. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I799aa1cd488a44b4ba9c198694f75d56b2294a03 Reviewed-on: http://git.am.freescale.net:8181/19711 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: remove M25PXX_USE_FAST_READ KconfigBrian Norris
Remove the compile-time option for FAST_READ, since we have run-time support for detecting it. This refactors the logic for enabling fast-read, such that for DT-enabled devices, we honor the "m25p,fast-read" property but for non-DT devices, we default to using FAST_READ whenever the flash device supports it. Normal READ and FAST_READ differ only in the following: * FAST_READ supports SPI higher clock frequencies [1] * number of dummy cycles; FAST_READ requires 8 dummy cycles (whereas READ requires 0) to allow the flash sufficient setup time, even when running at higher clock speeds Thus, for flash chips which support FAST_READ, there is otherwise no limiting reason why we cannot use the FAST_READ opcode instead of READ. It simply allows the SPI controller to run at higher clock rates. So theoretically, nobody should be needing the compile-time option anyway. [1] I have a Spansion S25FL128S datasheet which says: "The maximum operating clock frequency for the READ command is 50 MHz." And: "The maximum operating clock frequency for FAST READ command is 133 MHz." Signed-off-by: Brian Norris <computersforpeace@gmail.com> (cherry picked from commit ddba7c5ad797f4b878f4e177ef300c1f9837cd29) Change-Id: I205637becab372f43d3e8e741f20d35aac79a5fe Reviewed-on: http://git.am.freescale.net:8181/20036 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11mtd: m25p80: remove obsolete FIXMEBrian Norris
The FIXME and NOTE have already been fixed (we have FAST_READ support). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Sourav Poddar <sourav.poddar@ti.com> Acked-by: Marek Vasut <marex@denx.de> (cherry picked from commit 1a874e91018ea99d7f012a0824669aa9ed833d6f) Change-Id: I02d75e34033100678d65466628217bd493e82135 Reviewed-on: http://git.am.freescale.net:8181/20034 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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