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authorhongbo.wang <hongbo.wang@nxp.com>2017-05-02 08:31:21 (GMT)
committerXie Xiaobo <xiaobo.xie@nxp.com>2017-09-25 07:25:30 (GMT)
commit627e4b820d04e81e787c810fc1a280f50610be3b (patch)
tree9b665f86594f099355783a6d58b6951b284caffe
parent5be0fc5c16f3588d138aee7165f54abdb2fba01d (diff)
downloadlinux-627e4b820d04e81e787c810fc1a280f50610be3b.tar.xz
Disable ATU configuration and call dw_pcie_setup_rc in host_init function
Signed-off-by: hongbo.wang <hongbo.wang@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
-rw-r--r--drivers/pci/host/pci-layerscape.c15
-rw-r--r--drivers/pci/host/pcie-designware.c6
-rw-r--r--drivers/pci/host/pcie-designware.h1
3 files changed, 22 insertions, 0 deletions
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
index 6537079..80a8938 100644
--- a/drivers/pci/host/pci-layerscape.c
+++ b/drivers/pci/host/pci-layerscape.c
@@ -38,6 +38,10 @@
/* PEX LUT registers */
#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */
+#define PCIE_IATU_NUM 6
+
+static void ls_pcie_host_init(struct pcie_port *pp);
+
struct ls_pcie_drvdata {
u32 lut_offset;
u32 ltssm_shift;
@@ -86,6 +90,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
}
+static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
+{
+ int i;
+
+ for (i = 0; i < PCIE_IATU_NUM; i++)
+ dw_pcie_disable_outbound_atu(&pcie->pp, i);
+}
+
static int ls1021_pcie_link_up(struct pcie_port *pp)
{
u32 state;
@@ -153,6 +165,9 @@ static void ls_pcie_host_init(struct pcie_port *pp)
ls_pcie_clear_multifunction(pcie);
ls_pcie_drop_msg_tlp(pcie);
iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
+
+ ls_pcie_disable_outbound_atus(pcie);
+ dw_pcie_setup_rc(pp);
}
static int ls_pcie_msi_host_init(struct pcie_port *pp,
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index af8f6e9..2358e04 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -478,6 +478,12 @@ int dw_pcie_wait_for_link(struct pcie_port *pp)
return -ETIMEDOUT;
}
+void dw_pcie_disable_outbound_atu(struct pcie_port *pp, int index)
+{
+ dw_pcie_writel_rc(pp, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | index);
+ dw_pcie_writel_rc(pp, PCIE_ATU_CR2, 0);
+}
+
int dw_pcie_link_up(struct pcie_port *pp)
{
u32 val;
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index a567ea2..4e6672b 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -82,5 +82,6 @@ int dw_pcie_wait_for_link(struct pcie_port *pp);
int dw_pcie_link_up(struct pcie_port *pp);
void dw_pcie_setup_rc(struct pcie_port *pp);
int dw_pcie_host_init(struct pcie_port *pp);
+void dw_pcie_disable_outbound_atu(struct pcie_port *pp, int index);
#endif /* _PCIE_DESIGNWARE_H */