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authorVladimir Zapolskiy <vladimir_zapolskiy@mentor.com>2016-08-31 11:52:49 (GMT)
committerWim Van Sebroeck <wim@iguana.be>2016-09-24 07:27:12 (GMT)
commit68d4cb809ef84f9a0ea6a23c4c0dc0ae48355f78 (patch)
tree27a976c8bff6b9ac640beecc51c8baf1ac3bb269
parent7dd2ce7c91bd29d2fb7436cd2a607c7d24835e82 (diff)
downloadlinux-68d4cb809ef84f9a0ea6a23c4c0dc0ae48355f78.tar.xz
watchdog: imx2_wdt: use preferred BIT macro instead of open coded values
This is a nonfunctional change, declare register bit values with BIT() helper macro. The issues are reported by checkpatch: CHECK: Prefer using the BIT macro #40: FILE: drivers/watchdog/imx2_wdt.c:40: +#define IMX2_WDT_WCR_WDA (1 << 5) /* -> External Reset WDOG_B */ etc. Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
-rw-r--r--drivers/watchdog/imx2_wdt.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
index 62f346b..d17643e 100644
--- a/drivers/watchdog/imx2_wdt.c
+++ b/drivers/watchdog/imx2_wdt.c
@@ -37,18 +37,18 @@
#define IMX2_WDT_WCR 0x00 /* Control Register */
#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
-#define IMX2_WDT_WCR_WDA (1 << 5) /* -> External Reset WDOG_B */
-#define IMX2_WDT_WCR_SRS (1 << 4) /* -> Software Reset Signal */
-#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
-#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
-#define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */
+#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
+#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
+#define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
+#define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
+#define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
#define IMX2_WDT_WSR 0x02 /* Service Register */
#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
-#define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */
+#define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
#define IMX2_WDT_WMCR 0x08 /* Misc Register */