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| author | Alexander Shiyan <shc_work@mail.ru> | 2014-03-02 09:18:38 (GMT) |
|---|---|---|
| committer | Shawn Guo <shawn.guo@freescale.com> | 2014-04-30 05:35:18 (GMT) |
| commit | e8e8d621f90204d8293fd52bfdc3e957990cfa8f (patch) | |
| tree | 9884620eeb30db330bfb22abcc0263868a16f735 | |
| parent | 22970070e027cbbb9b2878f8f7c31d0d7f29e94d (diff) | |
| download | linux-e8e8d621f90204d8293fd52bfdc3e957990cfa8f.tar.xz | |
ARM: dts: imx27-phytec-phycore-rdk: Add missing pinctrl definition for SPI CS1
This patch adds missing pinctrl definition for SPI chipselect 1.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index df3b2e7..86510ed 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -15,6 +15,7 @@ }; &cspi1 { + pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, <&gpio4 27 GPIO_ACTIVE_LOW>; @@ -36,6 +37,12 @@ &iomuxc { imx27_phycore_rdk { + pinctrl_cspi1cs1: cspi1cs1grp { + fsl,pins = < + MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 + >; + }; + pinctrl_i2c1: i2c1grp { /* Add pullup to DATA line */ fsl,pins = < |