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| author | Nishanth Menon <nm@ti.com> | 2016-03-31 21:58:33 (GMT) |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2016-04-13 21:30:09 (GMT) |
| commit | f971512c78ee675c0308f1cda483a57e5de6769f (patch) | |
| tree | 3a4e603aced5a52660309a4a83fd1982e70f80e8 | |
| parent | e60ba933bc94b778425612c039a16b3acd4bf756 (diff) | |
| download | linux-f971512c78ee675c0308f1cda483a57e5de6769f.tar.xz | |
ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable core INA
Erratum i892 as will be documented in the upcoming G or later revision
of DRA7xx/ AM57xx errata documentation (SPRZ398F) states that L3 clock
needs to be kept active all the time to ensure that asymmetric aging
degradation is minimal and within the design allowed margin.
By allowing core domain to transition to INA and allowing L3 clock to be
turned off for extended periods of time, there is a risk of functional
issues and device failure as a result.
Ref: http://www.ti.com/lit/er/sprz429h/sprz429h.pdf
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
| -rw-r--r-- | arch/arm/mach-omap2/powerdomains7xx_data.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c index 287a203..f2b4557 100644 --- a/arch/arm/mach-omap2/powerdomains7xx_data.c +++ b/arch/arm/mach-omap2/powerdomains7xx_data.c @@ -160,7 +160,7 @@ static struct powerdomain core_7xx_pwrdm = { .name = "core_pwrdm", .prcm_offs = DRA7XX_PRM_CORE_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_INA_ON, + .pwrsts = PWRSTS_ON, .pwrsts_logic_ret = PWRSTS_RET, .banks = 5, .pwrsts_mem_ret = { |