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authorAndrzej Hajda <a.hajda@samsung.com>2015-10-20 09:22:33 (GMT)
committerSylwester Nawrocki <s.nawrocki@samsung.com>2016-02-03 10:03:50 (GMT)
commit02ed910cb4e1c3d03ef70efa94c08f5f580c7ff8 (patch)
treed3af3d76bd81191ab8c88fcf5a7e99a6f139bdf7
parent68b2206a57c22d5b7c5bb16308a4afafe04d416d (diff)
downloadlinux-02ed910cb4e1c3d03ef70efa94c08f5f580c7ff8.tar.xz
clk/samsung: exynos5433: add pclk_decon clock
This undocumented gate clock is used by DECON IP. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c2
-rw-r--r--include/dt-bindings/clock/exynos5433.h4
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 5530014..b7f1fb7 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2822,6 +2822,8 @@ static struct samsung_gate_clock disp_gate_clks[] __initdata = {
ENABLE_PCLK_DISP, 2, 0, 0),
GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
ENABLE_PCLK_DISP, 1, 0, 0),
+ GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
+ ENABLE_PCLK_DISP, 0, 0, 0),
/* ENABLE_SCLK_DISP */
GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 4f0d566..5c2636c 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -768,7 +768,9 @@
#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111
#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112
-#define DISP_NR_CLK 113
+#define CLK_PCLK_DECON 113
+
+#define DISP_NR_CLK 114
/* CMU_AUD */
#define CLK_MOUT_AUD_PLL_USER 1