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authorNathan Sullivan <nathan.sullivan@ni.com>2016-01-14 19:27:27 (GMT)
committerDavid S. Miller <davem@davemloft.net>2016-01-15 19:47:09 (GMT)
commit244683749e3c632ab45655098259d5514c179c8a (patch)
treeefe74e83c7ffcab7714e3ffe580f1d9209eb208f
parent65a5124a71e85c35fa8d047a471950325855dccf (diff)
downloadlinux-244683749e3c632ab45655098259d5514c179c8a.tar.xz
net: macb: clear interrupts when disabling them
Disabling interrupts with the IDR register does not stop the macb hardware from asserting its interrupt line if there are interrupts pending. Always clear the interrupts using ISR, and be sure to write it on hardware that is not read-to-clear, like Zynq. Not doing so will cause interrupts when the driver doesn't expect them. Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/cadence/macb.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index c563475..9d9984a 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1040,6 +1040,8 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
/* close possible race with dev_close */
if (unlikely(!netif_running(dev))) {
queue_writel(queue, IDR, -1);
+ if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
+ queue_writel(queue, ISR, -1);
break;
}
@@ -1561,6 +1563,8 @@ static void macb_reset_hw(struct macb *bp)
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
queue_writel(queue, IDR, -1);
queue_readl(queue, ISR);
+ if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
+ queue_writel(queue, ISR, -1);
}
}