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authorCarlos Santa <carlos.santa@intel.com>2016-08-17 19:30:45 (GMT)
committerRodrigo Vivi <rodrigo.vivi@intel.com>2016-09-07 23:07:08 (GMT)
commit33b5bf82a67bff6b494a76dcbc20bcbcf3a835ed (patch)
tree47bc3de598f3644d22c3ce01c62097af761298e5
parent86f3624bf2750d22a6d7290f625f2d11227edb21 (diff)
downloadlinux-33b5bf82a67bff6b494a76dcbc20bcbcf3a835ed.tar.xz
drm/i915: Move HAS_RC6p definition to platform definition
Moving all GPU features to the platform struct definition allows for - standard place when adding new features from new platforms - possible to see supported features when dumping struct definitions Signed-off-by: Carlos Santa <carlos.santa@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h3
-rw-r--r--drivers/gpu/drm/i915/i915_pci.c3
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c16e9cb..52ddad6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -659,6 +659,7 @@ struct intel_csr {
func(has_csr) sep \
func(has_resource_streamer) sep \
func(has_rc6) sep \
+ func(has_rc6p) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2792,7 +2793,7 @@ struct drm_i915_cmd_table {
#define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
#define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm)
#define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
-#define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+#define HAS_RC6p(dev) (INTEL_INFO(dev)->has_rc6p)
#define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 42108dc..c6a5bd0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -202,6 +202,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \
.has_rc6 = 1, \
+ .has_rc6p = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -221,6 +222,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \
.has_rc6 = 1, \
+ .has_rc6p = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
IVB_CURSOR_OFFSETS
@@ -264,6 +266,7 @@ static const struct intel_device_info intel_valleyview_info = {
.has_fpga_dbg = 1, \
.has_psr = 1, \
.has_resource_streamer = 1, \
+ .has_rc6p = 0 /* RC6p removed-by HSW */, \
.has_runtime_pm = 1
static const struct intel_device_info intel_haswell_info = {