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authorGabriel FERNANDEZ <gabriel.fernandez@st.com>2014-02-27 15:24:23 (GMT)
committerMike Turquette <mturquette@linaro.org>2014-03-25 22:59:31 (GMT)
commit43080568f7d5dc4e31d90246b9e80e9b4112975c (patch)
treea728aaaf3c248753fb384dabd75cf3cef4ce684f
parente83c4e4d19736a77e28ce3c87e5c9e6d6bd88773 (diff)
downloadlinux-43080568f7d5dc4e31d90246b9e80e9b4112975c.tar.xz
clk: st: Adds quadfs clock binding
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,quadfs.txt45
1 files changed, 45 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
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+Binding for a type of quad channel digital frequency synthesizer found on
+certain STMicroelectronics consumer electronics SoC devices.
+
+This version contains a programmable PLL which can generate up to 216, 432
+or 660MHz (from a 30MHz oscillator input) as the input to the digital
+synthesizers.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be:
+ "st,stih416-quadfs216", "st,quadfs"
+ "st,stih416-quadfs432", "st,quadfs"
+ "st,stih416-quadfs660-E", "st,quadfs"
+ "st,stih416-quadfs660-F", "st,quadfs"
+
+- #clock-cells : from common clock binding; shall be set to 1.
+
+- reg : A Base address and length of the register set.
+
+- clocks : from common clock binding
+
+- clock-output-names : From common clock binding. The block has 4
+ clock outputs but not all of them in a specific instance
+ have to be used in the SoC. If a clock name is left as
+ an empty string then no clock will be created for the
+ output associated with that string index. If fewer than
+ 4 strings are provided then no clocks will be created
+ for the remaining outputs.
+
+Example:
+
+ CLOCKGEN_E: CLOCKGEN_E {
+ #clock-cells = <1>;
+ compatible = "st,stih416-quadfs660-E", "st,quadfs";
+ reg = <0xfd3208bc 0xB0>;
+
+ clocks = <&CLK_SYSIN>;
+ clock-output-names = "CLK_M_PIX_MDTP_0",
+ "CLK_M_PIX_MDTP_1",
+ "CLK_M_PIX_MDTP_2",
+ "CLK_M_MPELPC";
+ };