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authorPatrice Chotard <patrice.chotard@st.com>2013-04-03 07:21:50 (GMT)
committerLinus Walleij <linus.walleij@linaro.org>2013-04-03 20:15:14 (GMT)
commit661462f4c6d3c9ae0bac193c65936ebfac4c95b4 (patch)
tree1e642db0fd52795d01819f69c5a3bf76d2bc39fb
parent6282c02e2cd1660f1b3ac64dfaa7f96a25cfa2a4 (diff)
downloadlinux-661462f4c6d3c9ae0bac193c65936ebfac4c95b4.tar.xz
pinctrl/abx500: fix ab9540 alternate function
This fix allows to correctly select default and alternate pin mode. By default for all ABx500 family chip, pin default mode is selected by clearing corresponding bit in GPIOSELx register except for pins which support alternate function, in this case, corresponding bit must be set. But, due to an unlogical hardware implementation, for one particular pin (GPIO11) reverse setting must be done. For that, update the alternate function array by declaring that this pin supports alternate function. Same issue has been fixed in pinctrl-ab8505.c Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--drivers/pinctrl/pinctrl-ab9540.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/pinctrl-ab9540.c b/drivers/pinctrl/pinctrl-ab9540.c
index 7610bd0..80f3173 100644
--- a/drivers/pinctrl/pinctrl-ab9540.c
+++ b/drivers/pinctrl/pinctrl-ab9540.c
@@ -393,7 +393,7 @@ struct alternate_functions ab9540alternate_functions[AB9540_GPIO_MAX_NUMBER + 1]
/* GPIOSEL2 - bits 0 and 3 are reserved */
ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */
ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */
- ALTERNATE_FUNCTIONS(11, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 1 */
+ ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 1 */
ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */
ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */
ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */