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author | Olof Johansson <olof@lixom.net> | 2013-08-29 20:21:24 (GMT) |
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committer | Olof Johansson <olof@lixom.net> | 2013-08-29 20:21:24 (GMT) |
commit | 66fafb6fbf03c8b0bb5978041ace3bce40821c4e (patch) | |
tree | 5e286317a5a42dbbd942187b74a9f9823ab53c76 | |
parent | b94c1823b872a3ab7f83e4adff7f02e6f47bb9ec (diff) | |
parent | 942f42214d693f98b6165d0202d21291f95bc37d (diff) | |
download | linux-66fafb6fbf03c8b0bb5978041ace3bce40821c4e.tar.xz |
Merge tag 'mmp-irq' of git://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into late/all
From Haojian Zhuang:
Move irq driver out of mach-mmp to support multiplatform
* tag 'mmp-irq' of git://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux:
irqchip: mmp: avoid to include irqs head file
ARM: mmp: avoid to include head file in mach-mmp
irqchip: mmp: support irqchip
irqchip: move mmp irq driver
-rw-r--r-- | arch/arm/Kconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-mmp/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/mach-mmp/common.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/entry-macro.S | 26 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/pxa168.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/pxa910.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-mmp/mmp-dt.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-mmp/mmp2-dt.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-mmp/mmp2.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-mmp/pxa910.c | 7 | ||||
-rw-r--r-- | drivers/irqchip/Makefile | 1 | ||||
-rw-r--r-- | drivers/irqchip/irq-mmp.c (renamed from arch/arm/mach-mmp/irq.c) | 338 | ||||
-rw-r--r-- | include/linux/irqchip/mmp.h | 6 |
13 files changed, 211 insertions, 195 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 43594d5..75e2eda 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -557,6 +557,7 @@ config ARCH_MMP select GENERIC_CLOCKEVENTS select GPIO_PXA select IRQ_DOMAIN + select MULTI_IRQ_HANDLER select NEED_MACH_GPIO_H select PINCTRL select PLAT_PXA diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 095c155..9b702a1 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -2,7 +2,7 @@ # Makefile for Marvell's PXA168 processors line # -obj-y += common.o devices.o time.o irq.o +obj-y += common.o devices.o time.o # SoC support obj-$(CONFIG_CPU_PXA168) += pxa168.o diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h index 991d7e9..cf445ba 100644 --- a/arch/arm/mach-mmp/common.h +++ b/arch/arm/mach-mmp/common.h @@ -3,7 +3,6 @@ extern void timer_init(int irq); -extern void __init icu_init_irq(void); extern void __init mmp_map_io(void); extern void mmp_restart(enum reboot_mode, const char *); extern void __init pxa168_clk_init(void); diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S deleted file mode 100644 index bd152e2..0000000 --- a/arch/arm/mach-mmp/include/mach/entry-macro.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * linux/arch/arm/mach-mmp/include/mach/entry-macro.S - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <asm/irq.h> -#include <mach/regs-icu.h> - - .macro get_irqnr_preamble, base, tmp - mrc p15, 0, \tmp, c0, c0, 0 @ CPUID - and \tmp, \tmp, #0xff00 - cmp \tmp, #0x5800 - ldr \base, =mmp_icu_base - ldr \base, [\base, #0] - addne \base, \base, #0x10c @ PJ1 AP INT SEL register - addeq \base, \base, #0x104 @ PJ4 IRQ SEL register - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \tmp, [\base, #0] - and \irqnr, \tmp, #0x3f - tst \tmp, #(1 << 6) - .endm diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index 459c2d0..a83ba7c 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -4,6 +4,7 @@ #include <linux/reboot.h> extern void pxa168_timer_init(void); +extern void __init icu_init_irq(void); extern void __init pxa168_init_irq(void); extern void pxa168_restart(enum reboot_mode, const char *); extern void pxa168_clear_keypad_wakeup(void); diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h index b914afa..9225320 100644 --- a/arch/arm/mach-mmp/include/mach/pxa910.h +++ b/arch/arm/mach-mmp/include/mach/pxa910.h @@ -2,6 +2,7 @@ #define __ASM_MACH_PXA910_H extern void pxa910_timer_init(void); +extern void __init icu_init_irq(void); extern void __init pxa910_init_irq(void); #include <linux/i2c.h> diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c index b37915d..cca529c 100644 --- a/arch/arm/mach-mmp/mmp-dt.c +++ b/arch/arm/mach-mmp/mmp-dt.c @@ -9,17 +9,13 @@ * publishhed by the Free Software Foundation. */ -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/of_irq.h> +#include <linux/irqchip.h> #include <linux/of_platform.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> -#include <mach/irqs.h> #include "common.h" -extern void __init mmp_dt_irq_init(void); extern void __init mmp_dt_init_timer(void); static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = { @@ -64,7 +60,6 @@ static const char *mmp_dt_board_compat[] __initdata = { DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)") .map_io = mmp_map_io, - .init_irq = mmp_dt_irq_init, .init_time = mmp_dt_init_timer, .init_machine = pxa168_dt_init, .dt_compat = mmp_dt_board_compat, @@ -72,7 +67,6 @@ MACHINE_END DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)") .map_io = mmp_map_io, - .init_irq = mmp_dt_irq_init, .init_time = mmp_dt_init_timer, .init_machine = pxa910_dt_init, .dt_compat = mmp_dt_board_compat, diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c index 4ac2567..023cb45 100644 --- a/arch/arm/mach-mmp/mmp2-dt.c +++ b/arch/arm/mach-mmp/mmp2-dt.c @@ -10,18 +10,13 @@ */ #include <linux/io.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/of_irq.h> +#include <linux/irqchip.h> #include <linux/of_platform.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> -#include <mach/irqs.h> -#include <mach/regs-apbc.h> #include "common.h" -extern void __init mmp_dt_irq_init(void); extern void __init mmp_dt_init_timer(void); static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = { @@ -49,7 +44,6 @@ static const char *mmp2_dt_board_compat[] __initdata = { DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)") .map_io = mmp_map_io, - .init_irq = mmp_dt_irq_init, .init_time = mmp_dt_init_timer, .init_machine = mmp2_dt_init, .dt_compat = mmp2_dt_board_compat, diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index c7592f1..a70b553 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c @@ -13,6 +13,8 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/irq.h> +#include <linux/irqchip/mmp.h> #include <linux/platform_device.h> #include <asm/hardware/cache-tauros2.h> @@ -26,6 +28,7 @@ #include <mach/mfp.h> #include <mach/devices.h> #include <mach/mmp2.h> +#include <mach/pm-mmp2.h> #include "common.h" @@ -94,6 +97,9 @@ void mmp2_clear_pmic_int(void) void __init mmp2_init_irq(void) { mmp2_init_icu(); +#ifdef CONFIG_PM + icu_irq_chip.irq_set_wake = mmp2_set_wake; +#endif } static int __init mmp2_init(void) diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index ce6393a..eb57ee1 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c @@ -12,6 +12,8 @@ #include <linux/init.h> #include <linux/list.h> #include <linux/io.h> +#include <linux/irq.h> +#include <linux/irqchip/mmp.h> #include <linux/platform_device.h> #include <asm/hardware/cache-tauros2.h> @@ -23,6 +25,8 @@ #include <mach/dma.h> #include <mach/mfp.h> #include <mach/devices.h> +#include <mach/pm-pxa910.h> +#include <mach/pxa910.h> #include "common.h" @@ -79,6 +83,9 @@ static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata = void __init pxa910_init_irq(void) { icu_init_irq(); +#ifdef CONFIG_PM + icu_irq_chip.irq_set_wake = pxa910_set_wake; +#endif } static int __init pxa910_init(void) diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e65c41a..c452943 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o +obj-$(CONFIG_ARCH_MMP) += irq-mmp.o obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o obj-$(CONFIG_ARCH_MXS) += irq-mxs.o obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o diff --git a/arch/arm/mach-mmp/irq.c b/drivers/irqchip/irq-mmp.c index 3c71246..2cb7cd0 100644 --- a/arch/arm/mach-mmp/irq.c +++ b/drivers/irqchip/irq-mmp.c @@ -21,19 +21,20 @@ #include <linux/of_address.h> #include <linux/of_irq.h> -#include <mach/irqs.h> +#include <asm/exception.h> +#include <asm/mach/irq.h> -#ifdef CONFIG_CPU_MMP2 -#include <mach/pm-mmp2.h> -#endif -#ifdef CONFIG_CPU_PXA910 -#include <mach/pm-pxa910.h> -#endif - -#include "common.h" +#include "irqchip.h" #define MAX_ICU_NR 16 +#define PJ1_INT_SEL 0x10c +#define PJ4_INT_SEL 0x104 + +/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */ +#define SEL_INT_PENDING (1 << 6) +#define SEL_INT_NUM_MASK 0x3f + struct icu_chip_data { int nr_irqs; unsigned int virq_base; @@ -54,7 +55,7 @@ struct mmp_intc_conf { unsigned int conf_mask; }; -void __iomem *mmp_icu_base; +static void __iomem *mmp_icu_base; static struct icu_chip_data icu_data[MAX_ICU_NR]; static int max_icu_nr; @@ -122,7 +123,7 @@ static void icu_unmask_irq(struct irq_data *d) } } -static struct irq_chip icu_irq_chip = { +struct irq_chip icu_irq_chip = { .name = "icu_irq", .irq_mask = icu_mask_irq, .irq_mask_ack = icu_mask_ack_irq, @@ -193,6 +194,32 @@ static struct mmp_intc_conf mmp2_conf = { .conf_mask = 0x7f, }; +static asmlinkage void __exception_irq_entry +mmp_handle_irq(struct pt_regs *regs) +{ + int irq, hwirq; + + hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL); + if (!(hwirq & SEL_INT_PENDING)) + return; + hwirq &= SEL_INT_NUM_MASK; + irq = irq_find_mapping(icu_data[0].domain, hwirq); + handle_IRQ(irq, regs); +} + +static asmlinkage void __exception_irq_entry +mmp2_handle_irq(struct pt_regs *regs) +{ + int irq, hwirq; + + hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL); + if (!(hwirq & SEL_INT_PENDING)) + return; + hwirq &= SEL_INT_NUM_MASK; + irq = irq_find_mapping(icu_data[0].domain, hwirq); + handle_IRQ(irq, regs); +} + /* MMP (ARMv5) */ void __init icu_init_irq(void) { @@ -214,15 +241,13 @@ void __init icu_init_irq(void) set_irq_flags(irq, IRQF_VALID); } irq_set_default_host(icu_data[0].domain); -#ifdef CONFIG_CPU_PXA910 - icu_irq_chip.irq_set_wake = pxa910_set_wake; -#endif + set_handle_irq(mmp_handle_irq); } /* MMP2 (ARMv7) */ void __init mmp2_init_icu(void) { - int irq; + int irq, end; max_icu_nr = 8; mmp_icu_base = ioremap(0xd4282000, 0x1000); @@ -236,11 +261,12 @@ void __init mmp2_init_icu(void) &icu_data[0]); icu_data[1].reg_status = mmp_icu_base + 0x150; icu_data[1].reg_mask = mmp_icu_base + 0x168; - icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE; - icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE; + icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base + + icu_data[0].nr_irqs; + icu_data[1].clr_mfp_hwirq = 1; /* offset to IRQ_MMP2_PMIC_BASE */ icu_data[1].nr_irqs = 2; icu_data[1].cascade_irq = 4; - icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE; + icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs; icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs, icu_data[1].virq_base, 0, &irq_domain_simple_ops, @@ -249,7 +275,7 @@ void __init mmp2_init_icu(void) icu_data[2].reg_mask = mmp_icu_base + 0x16c; icu_data[2].nr_irqs = 2; icu_data[2].cascade_irq = 5; - icu_data[2].virq_base = IRQ_MMP2_RTC_BASE; + icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs; icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs, icu_data[2].virq_base, 0, &irq_domain_simple_ops, @@ -258,7 +284,7 @@ void __init mmp2_init_icu(void) icu_data[3].reg_mask = mmp_icu_base + 0x17c; icu_data[3].nr_irqs = 3; icu_data[3].cascade_irq = 9; - icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE; + icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs; icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs, icu_data[3].virq_base, 0, &irq_domain_simple_ops, @@ -267,7 +293,7 @@ void __init mmp2_init_icu(void) icu_data[4].reg_mask = mmp_icu_base + 0x170; icu_data[4].nr_irqs = 5; icu_data[4].cascade_irq = 17; - icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE; + icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs; icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs, icu_data[4].virq_base, 0, &irq_domain_simple_ops, @@ -276,7 +302,7 @@ void __init mmp2_init_icu(void) icu_data[5].reg_mask = mmp_icu_base + 0x174; icu_data[5].nr_irqs = 15; icu_data[5].cascade_irq = 35; - icu_data[5].virq_base = IRQ_MMP2_MISC_BASE; + icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs; icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs, icu_data[5].virq_base, 0, &irq_domain_simple_ops, @@ -285,7 +311,7 @@ void __init mmp2_init_icu(void) icu_data[6].reg_mask = mmp_icu_base + 0x178; icu_data[6].nr_irqs = 2; icu_data[6].cascade_irq = 51; - icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE; + icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs; icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs, icu_data[6].virq_base, 0, &irq_domain_simple_ops, @@ -294,170 +320,176 @@ void __init mmp2_init_icu(void) icu_data[7].reg_mask = mmp_icu_base + 0x184; icu_data[7].nr_irqs = 2; icu_data[7].cascade_irq = 55; - icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE; + icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs; icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs, icu_data[7].virq_base, 0, &irq_domain_simple_ops, &icu_data[7]); - for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) { + end = icu_data[7].virq_base + icu_data[7].nr_irqs; + for (irq = 0; irq < end; irq++) { icu_mask_irq(irq_get_irq_data(irq)); - switch (irq) { - case IRQ_MMP2_PMIC_MUX: - case IRQ_MMP2_RTC_MUX: - case IRQ_MMP2_KEYPAD_MUX: - case IRQ_MMP2_TWSI_MUX: - case IRQ_MMP2_MISC_MUX: - case IRQ_MMP2_MIPI_HSI1_MUX: - case IRQ_MMP2_MIPI_HSI0_MUX: + if (irq == icu_data[1].cascade_irq || + irq == icu_data[2].cascade_irq || + irq == icu_data[3].cascade_irq || + irq == icu_data[4].cascade_irq || + irq == icu_data[5].cascade_irq || + irq == icu_data[6].cascade_irq || + irq == icu_data[7].cascade_irq) { irq_set_chip(irq, &icu_irq_chip); irq_set_chained_handler(irq, icu_mux_irq_demux); - break; - default: + } else { irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); - break; } set_irq_flags(irq, IRQF_VALID); } irq_set_default_host(icu_data[0].domain); -#ifdef CONFIG_CPU_MMP2 - icu_irq_chip.irq_set_wake = mmp2_set_wake; -#endif + set_handle_irq(mmp2_handle_irq); } #ifdef CONFIG_OF -static const struct of_device_id intc_ids[] __initconst = { - { .compatible = "mrvl,mmp-intc", .data = &mmp_conf }, - { .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf }, - {} -}; - -static const struct of_device_id mmp_mux_irq_match[] __initconst = { - { .compatible = "mrvl,mmp2-mux-intc" }, - {} -}; - -int __init mmp2_mux_init(struct device_node *parent) +static int __init mmp_init_bases(struct device_node *node) { - struct device_node *node; - const struct of_device_id *of_id; - struct resource res; - int i, irq_base, ret, irq; - u32 nr_irqs, mfp_irq; + int ret, nr_irqs, irq, i = 0; - node = parent; - max_icu_nr = 1; - for (i = 1; i < MAX_ICU_NR; i++) { - node = of_find_matching_node(node, mmp_mux_irq_match); - if (!node) - break; - of_id = of_match_node(&mmp_mux_irq_match[0], node); - ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", - &nr_irqs); - if (ret) { - pr_err("Not found mrvl,intc-nr-irqs property\n"); - ret = -EINVAL; - goto err; - } - ret = of_address_to_resource(node, 0, &res); - if (ret < 0) { - pr_err("Not found reg property\n"); - ret = -EINVAL; - goto err; - } - icu_data[i].reg_status = mmp_icu_base + res.start; - ret = of_address_to_resource(node, 1, &res); - if (ret < 0) { - pr_err("Not found reg property\n"); - ret = -EINVAL; - goto err; - } - icu_data[i].reg_mask = mmp_icu_base + res.start; - icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0); - if (!icu_data[i].cascade_irq) { - ret = -EINVAL; - goto err; - } + ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs); + if (ret) { + pr_err("Not found mrvl,intc-nr-irqs property\n"); + return ret; + } + + mmp_icu_base = of_iomap(node, 0); + if (!mmp_icu_base) { + pr_err("Failed to get interrupt controller register\n"); + return -ENOMEM; + } - irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); - if (irq_base < 0) { - pr_err("Failed to allocate IRQ numbers for mux intc\n"); - ret = irq_base; + icu_data[0].virq_base = 0; + icu_data[0].domain = irq_domain_add_linear(node, nr_irqs, + &mmp_irq_domain_ops, + &icu_data[0]); + for (irq = 0; irq < nr_irqs; irq++) { + ret = irq_create_mapping(icu_data[0].domain, irq); + if (!ret) { + pr_err("Failed to mapping hwirq\n"); goto err; } - if (!of_property_read_u32(node, "mrvl,clr-mfp-irq", - &mfp_irq)) { - icu_data[i].clr_mfp_irq_base = irq_base; - icu_data[i].clr_mfp_hwirq = mfp_irq; - } - irq_set_chained_handler(icu_data[i].cascade_irq, - icu_mux_irq_demux); - icu_data[i].nr_irqs = nr_irqs; - icu_data[i].virq_base = irq_base; - icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs, - irq_base, 0, - &mmp_irq_domain_ops, - &icu_data[i]); - for (irq = irq_base; irq < irq_base + nr_irqs; irq++) - icu_mask_irq(irq_get_irq_data(irq)); + if (!irq) + icu_data[0].virq_base = ret; } - max_icu_nr = i; + icu_data[0].nr_irqs = nr_irqs; return 0; err: - of_node_put(node); - max_icu_nr = i; - return ret; + if (icu_data[0].virq_base) { + for (i = 0; i < irq; i++) + irq_dispose_mapping(icu_data[0].virq_base + i); + } + irq_domain_remove(icu_data[0].domain); + iounmap(mmp_icu_base); + return -EINVAL; } -void __init mmp_dt_irq_init(void) +static int __init mmp_of_init(struct device_node *node, + struct device_node *parent) { - struct device_node *node; - const struct of_device_id *of_id; - struct mmp_intc_conf *conf; - int nr_irqs, irq_base, ret, irq; - - node = of_find_matching_node(NULL, intc_ids); - if (!node) { - pr_err("Failed to find interrupt controller in arch-mmp\n"); - return; - } - of_id = of_match_node(intc_ids, node); - conf = of_id->data; + int ret; - ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs); + ret = mmp_init_bases(node); + if (ret < 0) + return ret; + + icu_data[0].conf_enable = mmp_conf.conf_enable; + icu_data[0].conf_disable = mmp_conf.conf_disable; + icu_data[0].conf_mask = mmp_conf.conf_mask; + irq_set_default_host(icu_data[0].domain); + set_handle_irq(mmp_handle_irq); + max_icu_nr = 1; + return 0; +} +IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init); + +static int __init mmp2_of_init(struct device_node *node, + struct device_node *parent) +{ + int ret; + + ret = mmp_init_bases(node); + if (ret < 0) + return ret; + + icu_data[0].conf_enable = mmp2_conf.conf_enable; + icu_data[0].conf_disable = mmp2_conf.conf_disable; + icu_data[0].conf_mask = mmp2_conf.conf_mask; + irq_set_default_host(icu_data[0].domain); + set_handle_irq(mmp2_handle_irq); + max_icu_nr = 1; + return 0; +} +IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init); + +static int __init mmp2_mux_of_init(struct device_node *node, + struct device_node *parent) +{ + struct resource res; + int i, ret, irq, j = 0; + u32 nr_irqs, mfp_irq; + + if (!parent) + return -ENODEV; + + i = max_icu_nr; + ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", + &nr_irqs); if (ret) { pr_err("Not found mrvl,intc-nr-irqs property\n"); - return; + return -EINVAL; } - - mmp_icu_base = of_iomap(node, 0); - if (!mmp_icu_base) { - pr_err("Failed to get interrupt controller register\n"); - return; + ret = of_address_to_resource(node, 0, &res); + if (ret < 0) { + pr_err("Not found reg property\n"); + return -EINVAL; } - - irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0); - if (irq_base < 0) { - pr_err("Failed to allocate IRQ numbers\n"); - goto err; - } else if (irq_base != NR_IRQS_LEGACY) { - pr_err("ICU's irqbase should be started from 0\n"); - goto err; + icu_data[i].reg_status = mmp_icu_base + res.start; + ret = of_address_to_resource(node, 1, &res); + if (ret < 0) { + pr_err("Not found reg property\n"); + return -EINVAL; } - icu_data[0].conf_enable = conf->conf_enable; - icu_data[0].conf_disable = conf->conf_disable; - icu_data[0].conf_mask = conf->conf_mask; - icu_data[0].nr_irqs = nr_irqs; - icu_data[0].virq_base = 0; - icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0, + icu_data[i].reg_mask = mmp_icu_base + res.start; + icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0); + if (!icu_data[i].cascade_irq) + return -EINVAL; + + icu_data[i].virq_base = 0; + icu_data[i].domain = irq_domain_add_linear(node, nr_irqs, &mmp_irq_domain_ops, - &icu_data[0]); - irq_set_default_host(icu_data[0].domain); - for (irq = 0; irq < nr_irqs; irq++) - icu_mask_irq(irq_get_irq_data(irq)); - mmp2_mux_init(node); - return; + &icu_data[i]); + for (irq = 0; irq < nr_irqs; irq++) { + ret = irq_create_mapping(icu_data[i].domain, irq); + if (!ret) { + pr_err("Failed to mapping hwirq\n"); + goto err; + } + if (!irq) + icu_data[i].virq_base = ret; + } + icu_data[i].nr_irqs = nr_irqs; + if (!of_property_read_u32(node, "mrvl,clr-mfp-irq", + &mfp_irq)) { + icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base; + icu_data[i].clr_mfp_hwirq = mfp_irq; + } + irq_set_chained_handler(icu_data[i].cascade_irq, + icu_mux_irq_demux); + max_icu_nr++; + return 0; err: - iounmap(mmp_icu_base); + if (icu_data[i].virq_base) { + for (j = 0; j < irq; j++) + irq_dispose_mapping(icu_data[i].virq_base + j); + } + irq_domain_remove(icu_data[i].domain); + return -EINVAL; } +IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init); #endif diff --git a/include/linux/irqchip/mmp.h b/include/linux/irqchip/mmp.h new file mode 100644 index 0000000..c78a892 --- /dev/null +++ b/include/linux/irqchip/mmp.h @@ -0,0 +1,6 @@ +#ifndef __IRQCHIP_MMP_H +#define __IRQCHIP_MMP_H + +extern struct irq_chip icu_irq_chip; + +#endif /* __IRQCHIP_MMP_H */ |