diff options
| author | Lucas Stach <l.stach@pengutronix.de> | 2014-03-28 16:52:58 (GMT) |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2014-05-30 17:24:58 (GMT) |
| commit | 7f4f16eef5aeba31bdfb7702ced06a42f2777e04 (patch) | |
| tree | a10b8f076e0278742ba80181b2d3d3fba56777ad | |
| parent | 5c40eea7783bbcdd5795cd7d50b7b3fd9a94dc94 (diff) | |
| download | linux-7f4f16eef5aeba31bdfb7702ced06a42f2777e04.tar.xz | |
PCI: designware: Make MSI ISR shared IRQ aware
On i.MX6 the host controller MSI IRQ is shared with PCI legacy INTD. Make
sure we don't bail too early from the IRQ handler.
The issue is fairly theoretical as it would require a system setup with a
PCIe switch where one connected device is using legacy INTD and another one
using MSI, but better fix it now.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Richard Zhu <r65037@freescale.com>
| -rw-r--r-- | drivers/pci/host/pci-exynos.c | 4 | ||||
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 6 | ||||
| -rw-r--r-- | drivers/pci/host/pcie-designware.h | 2 |
3 files changed, 7 insertions, 5 deletions
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 3de6bfb..b616d34 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -415,9 +415,7 @@ static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg) { struct pcie_port *pp = arg; - dw_handle_msi_irq(pp); - - return IRQ_HANDLED; + return dw_handle_msi_irq(pp); } static void exynos_pcie_msi_init(struct pcie_port *pp) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 509a29d..77a649d 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -155,15 +155,17 @@ static struct irq_chip dw_msi_irq_chip = { }; /* MSI int handler */ -void dw_handle_msi_irq(struct pcie_port *pp) +irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) { unsigned long val; int i, pos, irq; + irqreturn_t ret = IRQ_NONE; for (i = 0; i < MAX_MSI_CTRLS; i++) { dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, (u32 *)&val); if (val) { + ret = IRQ_HANDLED; pos = 0; while ((pos = find_next_bit(&val, 32, pos)) != 32) { irq = irq_find_mapping(pp->irq_domain, @@ -176,6 +178,8 @@ void dw_handle_msi_irq(struct pcie_port *pp) } } } + + return ret; } void dw_pcie_msi_init(struct pcie_port *pp) diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index 3063b35..a169d22 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -68,7 +68,7 @@ struct pcie_host_ops { int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val); int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val); -void dw_handle_msi_irq(struct pcie_port *pp); +irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); void dw_pcie_msi_init(struct pcie_port *pp); int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); |