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authoryinbo.zhu <yinbo.zhu@nxp.com>2017-10-25 09:41:09 (GMT)
committerXie Xiaobo <xiaobo.xie@nxp.com>2017-12-12 07:32:40 (GMT)
commit946747446edd2ec83abb653aaf64c7a031fd9097 (patch)
treead0f7231b18763a3fcac573b9616217efff1d340
parente51ae985273348fbaffffa58c0e3eca9a0ab773e (diff)
downloadlinux-946747446edd2ec83abb653aaf64c7a031fd9097.tar.xz
mmc: sdhci-of-esdhc: Workaround for reducing the maximum speed on ls1021atwr
In SDHC high speed AC timing, the tshivkh parameter is defined as input setup times:SDHC_CMD, SDHC_DATx, to SDHC_CLK. The value of the tshivkh should be 2.5 ns considering the round trip delay, board/data skew. However, because of this erratum, it needs at least 4.1 ns. eSDHC cannot run at the maximum clock speed for the high speed mode, or there is a limit on the length of the trace on the board for data, command, and clock lines of the SDHC. Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
-rw-r--r--drivers/mmc/host/sdhci-of-esdhc.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index bfa0582..4aaa790 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -502,6 +502,12 @@ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
clock -= 5000000;
}
+ /* Workaround to reduce the clock frequency for ls1021a esdhc */
+ if (of_find_compatible_node(NULL, NULL, "fsl,ls1021a-esdhc")) {
+ if (clock == 50000000)
+ clock = 46500000;
+ }
+
temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);