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authorMaciej W. Rozycki <macro@linux-mips.org>2015-05-27 13:15:20 (GMT)
committerRalf Baechle <ralf@linux-mips.org>2015-06-21 19:52:41 (GMT)
commit9a20b09285bbd75ccc2ca78233241f8e31d54a28 (patch)
treef18914b5a7e902428a14a9b58025d64ff950d64e
parent3bcb03f3a7160e411c5f335028a5c70b32f0edb7 (diff)
downloadlinux-9a20b09285bbd75ccc2ca78233241f8e31d54a28.tar.xz
MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation
Replace an explicit barrier with a useful processor instruction in TLB invalidation, following several other such cases elsewhere in `tlb-r3k.c'. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10196/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/mm/tlb-r3k.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index 49b7132..2b75b8f 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -45,10 +45,10 @@ static void local_flush_tlb_from(int entry)
old_ctx = read_c0_entryhi() & ASID_MASK;
write_c0_entrylo0(0);
- for (; entry < current_cpu_data.tlbsize; entry++) {
+ while (entry < current_cpu_data.tlbsize) {
write_c0_index(entry << 8);
write_c0_entryhi((entry | 0x80000) << 12);
- BARRIER;
+ entry++; /* BARRIER */
tlb_write_indexed();
}
write_c0_entryhi(old_ctx);