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author | Yunzhi Li <lyz@rock-chips.com> | 2015-01-21 10:26:00 (GMT) |
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committer | Kishon Vijay Abraham I <kishon@ti.com> | 2015-01-30 10:36:47 (GMT) |
commit | 9b43e5ec89dd0c863959ae0157ad3d693588ab44 (patch) | |
tree | 336240a7c5612ba0d13e6d5105c87307802dc7db | |
parent | 5402d927ae96bd1413ecc6bac966fd8b6d3b8159 (diff) | |
download | linux-9b43e5ec89dd0c863959ae0157ad3d693588ab44.tar.xz |
Documentation: bindings: add dt documentation for Rockchip usb PHY
This patch adds a binding that describes the Rockchip usb PHYs
found on Rockchip SoCs usb interface.
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
-rw-r--r-- | Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt new file mode 100644 index 0000000..826454a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt @@ -0,0 +1,37 @@ +ROCKCHIP USB2 PHY + +Required properties: + - compatible: rockchip,rk3288-usb-phy + - rockchip,grf : phandle to the syscon managing the "general + register files" + - #address-cells: should be 1 + - #size-cells: should be 0 + +Sub-nodes: +Each PHY should be represented as a sub-node. + +Sub-nodes +required properties: +- #phy-cells: should be 0 +- reg: PHY configure reg address offset in GRF + "0x320" - for PHY attach to OTG controller + "0x334" - for PHY attach to HOST0 controller + "0x348" - for PHY attach to HOST1 controller + +Optional Properties: +- clocks : phandle + clock specifier for the phy clocks +- clock-names: string, clock name, must be "phyclk" + +Example: + +usbphy: phy { + compatible = "rockchip,rk3288-usb-phy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usb-phy0 { + #phy-cells = <0>; + reg = <0x320>; + }; +}; |