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authorEric Miao <ycmiao@ycmiao-hp520.(none)>2008-12-18 14:10:00 (GMT)
committerEric Miao <eric.miao@marvell.com>2008-12-29 09:59:17 (GMT)
commita0427509a76c61984fbba4e206b617c689f419ef (patch)
treee7b7f74b912ae35677767213c77308c3e9c4d64e
parent6e354846e807e037751fdc8faaee8ad492177113 (diff)
downloadlinux-a0427509a76c61984fbba4e206b617c689f419ef.tar.xz
[ARM] pxafb: add palette format support for LCCR4_PAL_FOR_3
Add the palette format support for LCCR4_PAL_FOR_3, and fix the issue of LCCR4 being never assigned. Also remove the useless pxafb_set_truecolor(). Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Eric Miao <ycmiao@ycmiao-hp520.(none)>
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-lcd.h1
-rw-r--r--drivers/video/pxafb.c21
2 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h
index c15df55..5c52226 100644
--- a/arch/arm/mach-pxa/include/mach/regs-lcd.h
+++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h
@@ -48,6 +48,7 @@
#define LCCR4_PAL_FOR_0 (0 << 15)
#define LCCR4_PAL_FOR_1 (1 << 15)
#define LCCR4_PAL_FOR_2 (2 << 15)
+#define LCCR4_PAL_FOR_3 (3 << 15)
#define LCCR4_PAL_FOR_MASK (3 << 15)
#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index b43907d..c57f909 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -155,6 +155,12 @@ pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
val |= ((blue >> 8) & 0x000000fc);
((u32 *)(fbi->palette_cpu))[regno] = val;
break;
+ case LCCR4_PAL_FOR_3:
+ val = ((red << 8) & 0x00ff0000);
+ val |= ((green >> 0) & 0x0000ff00);
+ val |= ((blue >> 8) & 0x000000ff);
+ ((u32 *)(fbi->palette_cpu))[regno] = val;
+ break;
}
return 0;
@@ -416,11 +422,6 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
return 0;
}
-static inline void pxafb_set_truecolor(u_int is_true_color)
-{
- /* do your machine-specific setup if needed */
-}
-
/*
* pxafb_set_par():
* Set the user defined part of the display for the specified console
@@ -453,11 +454,6 @@ static int pxafb_set_par(struct fb_info *info)
fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
- /*
- * Set (any) board control register to handle new color depth
- */
- pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
-
if (fbi->fb.var.bits_per_pixel >= 16)
fb_dealloc_cmap(&fbi->fb.cmap);
else
@@ -727,6 +723,7 @@ int pxafb_smart_flush(struct fb_info *info)
lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
+ lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
@@ -995,6 +992,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
(lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
(lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
(lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
+ (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
(lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
(lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
pxafb_schedule_work(fbi, C_REENABLE);
@@ -1041,6 +1039,7 @@ static void pxafb_enable_controller(struct pxafb_info *fbi)
return;
/* Sequence from 11.7.10 */
+ lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
@@ -1313,6 +1312,7 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
fbi->cmap_inverse = inf->cmap_inverse;
fbi->cmap_static = inf->cmap_static;
+ fbi->lccr4 = inf->lccr4;
switch (lcd_conn & LCD_TYPE_MASK) {
case LCD_TYPE_MONO_STN:
@@ -1337,7 +1337,6 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
/* fall back to backward compatibility way */
fbi->lccr0 = inf->lccr0;
fbi->lccr3 = inf->lccr3;
- fbi->lccr4 = inf->lccr4;
goto decode_mode;
}