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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-09-30 13:22:15 (GMT) |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-02-17 05:53:08 (GMT) |
| commit | a528b4bf1a2ecb756aa65548fd5518fe82fb4648 (patch) | |
| tree | f715e062d0bd2879e69ad2bebb30203b01b53ec3 | |
| parent | 52b541abbc02f64e2105dff278c8b4e7e75041f4 (diff) | |
| download | linux-a528b4bf1a2ecb756aa65548fd5518fe82fb4648.tar.xz | |
arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node
Add the missing "cache-unified" and "cache-level" properties to the
Cortex-A57 cache-controller node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 832a566..ea56066 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -68,6 +68,8 @@ L2_CA57: cache-controller@0 { compatible = "cache"; + cache-unified; + cache-level = <2>; }; extal_clk: extal { |